The original plan of YMTC was to build Fab 1, and eventually expand the site with another two Fabs (2 and 3). Each fab was originally planned to have 100K wafers per month capacity. 300K wafers per month total capacity with all three fabs when the site is complete. If you look at the satellite photos, Fab 1 and Fab 2 have been built and "Fab 3" is still a vacant lot with no building in it.
Fab 2 last I checked seemed to have half the air conditioner units attached to the building operational. I would guess that Fab 1 is fully operational with 100K wafers per month, and Fab 2 likely is operating at half capacity with 50K wafers per month. So my guess would be 150K wafers per month total right now.
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The issue is how many of those 150K are 232L NAND wafers per month using this XTacking 3.0 technology.
XTACKING ARCHITECTURE: YMTC’S NAND MEMORY CENTERPIECE
At the very heart of the manufacture of all YMTC’s 3D NAND chips is the Xtacking approach. Known as YMTC’s hallmark, Xtacking involves the use of two separate wafers, whereas only one wafer is traditionally employed. It consists of building the NAND dies by joining a CMOS wafer and a NAND array wafer face to face, the two wafers being bonded together using metal pads. Both wafers can be manufactured simultaneously, enabling the manufacturer to shorten the production cycle in case of high memory demand.
A cross-sectional view of the die shows that two decks of alternating tungsten wordlines and SiO layers are formed one after the other. This method was adopted to reduce high aspect ratio etching. If built in one deck, the etch channel aspect ratio would have been 109:1, which would have resulted in very complex trench etching and filling processes and a higher etch defect number.
-Due etching ratios constrains look like they have to built the decks in stages, depending on the etching equipment the are using AMEC 3DNAND etchers or mature LAM etchers or advanced LAM etchers, will affect the final yield. Another factor is WCVD tools, AMEC launched their WCVD tools this year but remain to see how their deposition rate is compared to banned tools or if YMTC have enough banned tools as disposal.
The strategy is always to find the right balance between yield losses and the cost induced by repeating the etching process. Two hundred fifty-three wordlines are observed in the vertical NAND string; 128 layers form Deck 1 and 125 form deck 2. Besides the 232 active layers, the remaining ones are divided between dummy and selection layers.
Yole SystemPlus identified the use of a hybrid direct bonding technique to build chemical-free copper-to-copper interconnects that join the wafers together introduced by YMTC in memory manufacturing. Physical interaction between the dielectric material and the copper metal from the two wafers forms a strong bond. The bonding interface is further strengthened by plasma treatment of the surfaces and a thermal/annealing process. With this technique, YMTC is able to scale the bonding pad pitch down to 0.8 µm. In addition, accurate pad alignment is observed, with a pad mismatch of 22 nm representing only 6% of the pad surface.
