Systematical Investigation of Flicker Noise in 14 nm FinFET Devices towards Stochastic Computing Application
1- State Key Laboratory of Fabrication Technologies for Integrated Circuits, Institute of Microelectronics of the Chinese Academy of Sciences, Beijing 100029, China
2-School of Microelectronics, University of Chinese Academy of Sciences (UCAS), Beijing 101408, China
3-School of Microelectronics, University of Science and Technology of China, Hefei 230026, China
4-College of Communication Engineering (College of Microelectronics), Chengdu University of Information Technology, Chengdu 610225, China
Abstract
Stochastic computing (SC) is widely known for its high error tolerance and efficient computing ability of complex functions with remarkably simple logic gates. The noise of electronic devices is widely used to be the entropy source due to its randomness. Compared with thermal noise and random telegraph noise (RTN), flicker noise is favored by researchers because of its high noise density. Meanwhile, unlike using RRAM, PCRAM and other emerging memory devices as the entropy source, using logic devices does not require any additional process steps, which is significant for industrialization. In this work, we systematically and statistically studied the 1/f noise characteristics of 14 nm FinFET, and found that miniaturizing the channel area of the device or lowering the ambient temperature can effectively increase the 1/f noise density of the device. This is of great importance to improve the accuracy of the SC system and simplify the complexity of the stochastic number generator (SNG) circuit. At the same time, these rules of 1/f noise characteristics in FinFET devices can provide good guidance for our device selection in circuit design.
2. Device Fabrication and Experiments
The FinFET devices are fabricated based on the Semiconductor Manufacturing International Corporation (SMIC) 14 nm FinFET CMOS process platform. The Fin width (Tfin) and height (Hfin) were 12 nm and 21 nm, respectively, and the effective device width was approximately given by Nfinger × Nfin × (2 × Hfin + Tfin). So, the channel area of the FinFET device is calculated as follows:
Here, A is the channel area, Weff is the effective device width, and L is the channel length