Your had made two mistakes:SMIC's N+2 process is supposed to have 113.6 million transistors per sq millimeter. This is basically the same as TSMC's N7+ using EUV in critical layers with 113.9 MTr/mm2. Compare that with when TSMC was still only using DUV. DUV only N7 process had 91.2 MTr/mm2.
SMIC's N+2 is slightly better in terms of density than Samsung's 6LPP process which has 112.79 MTr/mm2. It also compares much favorably in terms of density with Intel 7 which only has 100.76 MTr/mm2.
SMIC's N+2 is basically on the 6 nm intermediate node class in terms of transistor density. You could argue that in terms of transistor density SMIC is right now ahead of Intel until the Intel 4 process enters the market.
HiSilicon used the SMIC N+2 process in the Kirin 9000S. But they also used their own core design with two-way SMT. This means each core has higher multi-threaded performance than competing ARM core designs in the same process. This enables the processor to be competitive against 5 nm designs.
TSMC 7nm+ basic cell size is 171x240nm
SMIC N+2 is 180x252nm. so your claim that N+2 share the same transistor density with TSMC 7nm+ is incorrect. If you use Apple-to-Apple calculation of assuming 60% NAND cell and 40% SFF cells, N+2 would have transistor density of about 103MTx/mma^2
(and if you use TechInsight's CPP measurement off the Kirin9000s, which is 63nm, instead of 60nm (which is what I used), then N+2 would have cell size of 189x252nm with corresponding transistor density of 98.1 MTx/mm^2).
Intel 10nm density is 100.76MTx/mm^2. The improved and newly named Intel7 has smaller cell size so has density of around 106MTx/mm^2.
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