Chinese semiconductor industry

Xinyuan Micro (KingSemi) announced that the company’s wholly-owned subsidiary Shanghai Xinyuan Micro Enterprise Development Co., Ltd. registered capital increased from RMB 300 million to RMB 520 million, an increase of 73.33%.

The business scope was changed from: sales of special equipment for semiconductor devices, sales of special electronic equipment, research and development of special electronic materials, engineering management services, etc., to: manufacturing of special electronic equipment, sales of special electronic equipment, manufacturing of special equipment for semiconductor devices , sales of special equipment for semiconductor devices, Electronic special materials research and development, mechanical parts / parts processing , mechanical parts / parts sales , engineering management services, etc.

Is more than adding more transistors, a good architectural design can deliver a good performance than just dimensional scaling.

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Let’s start with a bit of a background. In a presented at the 2017 IEEE S3S conference, titled “A 1,000x Improvement in Computer Systems by Bridging the Processor-Memory Gap,” we introduced the potential of using hybrid bonding to overcome the “Memory Wall.” We further elaborated on this concept in a , titled “A 1000× Improvement of the Processor-Memory Gap,” published in the book NANO-CHIPS 2030,published in 2020.

On June 15, 2022, a Chinese titled “Breakthrough Bypassing the EUV Lithography Machine to Realize the Independent Development of DRAM Chips” reported that Xinmeng Technology had announced the development of a 3D 4F² DRAM architecture based on its HITOC technology. The company claimed that this architecture could be used as an alternative to advanced commercial DRAM. According to the article, this development represents another major innovation breakthrough in the field of heterogeneous integration technology, following the release of SUNRISE, an all-in-one AI chip for storage and computing. The article also reported that Haowei Technology had successfully used Xinmeng’s HITOC technology for the latest tape-out of the Cuckoo 2 chip, resulting in a large-capacity storage-computing integrated 3D architecture.

Techinsights is currently promoting a titled “China breaks through restrictions with advanced chiplet strategy: 3D-IC Breakthrough in Chinese Ethereum Miner.” According to the report, Techinsights discovered a storage mining design in the Jasminer X4 Ethereum miner ASIC, which was developed by the China-based manufacturer Jasminer. The report states that this design is the industry’s first-ever use of DBI hybrid bonding technology with DRAM. Techinsights highlights that the Jasminer X4 demonstrates how a Chinese company can combine mature technologies to creatively produce high-performance, cutting-edge applications even under trade restrictions. The report also reveals that the X4 features a sizable 32 mm × 21 mm logic die that employs the earlier XMC (Wuhan Xinxin Semiconductor Manufacturing Co.) planar 40/45 nm CMOS.

Recently, the Zhejiang Provincial Development and Reform Commission issued the "Notice of the Provincial Development and Reform Commission on Identifying the List of Provincial Engineering Research Centers in 2023." Under the leadership of the Science and Technology Innovation Center of Zhejiang University, Silicon Power has jointly established the Zhejiang Provincial Engineering Research Center for Wide Bandgap Power Devices and Applications in conjunction with Shaoxing Semiconductor Manufacturing Co., Ltd., Zhejiang Fute Technology Co., Ltd. and Maitian Energy Co., Ltd. Successfully approved.​

　　Zhu Huilong’s research team at the Institute of Microelectronics’ Integrated Circuit Leading Process R&D Center first proposed a self-aligned metal gate vertical gate-all-around nanotransistor in 2016 and conducted a systematic study on it. It has achieved great results in terms of device structure, process, integration technology and application. Through a series of progress and breakthroughs, the research and development results such as VSAFET , VCNFET , Fe-VSAFET , and 3D NOR have been published in top international journals in the field of microelectronic devices, and have been featured as covers or "Editor's Choice" articles many times.

　　Recently, the team used a self-developed self-limiting ALE ( atomic layer etching ) process to achieve dual selective and precise etching of germanium-silicon materials and crystal planes by germanium , and prepared a silicon wafer composed of (111) crystal planes. Hourglass-shaped single crystal Ge channel self-aligned vertical nanometer gate-all-around device. The narrowest point of this hourglass-shaped Ge channel device is 5-20nm, showing excellent immunity to short channel effects and other excellent properties . The on-state current (I on ) of the nanowire device reaches 291μA/μm , which is the largest among similar devices. The device also has a high current switching ratio (I on /I off = 3.1×10 6 ) , good sub-threshold swing (SS = 91 mV/dec ) and drain-induced barrier reduction (DIBL = 55mV/V ) . Relevant research results were published in ACS NANO , a top journal in engineering technology ( 2023 Impact Factor /JCR Division: 17.1/Q1 ) (DOI: 10.1021/acsnano.3c02518). Xie Lu, a doctoral student at the Pioneer Center, is the first author of the article , and Researcher Zhu Huilong He and Senior Engineer Zhang Yongkui are the co-corresponding authors.

　　The research was funded by the Strategic Priority Project of the Chinese Academy of Sciences, the Youth Innovation Promotion Association of the Chinese Academy of Sciences, the Beijing Superstring Memory Institute, and the National Natural Science Foundation of China.