Interesting 1999 article about the history of EUV and what lies ahead potentially
Chinese semiconductor industry
- Thread starter Hendrik_2000
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Looks like a case of making a step so big that it tore the balls.
Total investment 700 million yuan? Standard Semiconductor Intelligent Equipment Production Center is capped.
Biaopu Semiconductor shows that the project was invested, developed and constructed by Biaopu Semiconductor Technology (Dongguan City) Co., Ltd., covering an area of 26,000 square meters, with a total construction area of approximately 100,000 square meters, including two 10-story high-standard factory buildings and one A 16-story modern dormitory building with 400 underground parking spaces.In November 2022, a groundbreaking ceremony was held for the Biaopu Semiconductor Intelligent Equipment Production Center project in Changping Town, Dongguan. News at the time showed that the project had a total investment of 700 million yuan and was signed in May 2022 to settle in Changping Town. It is mainly engaged in the research and development, production and sales of semiconductor automation equipment. The products include semiconductor automation equipment, spectroscopic color separation machines and automatic packaging machines.
5.1 billion yuan, 360,000 pieces! 2 SiC projects signed/activated
On September 26, Hunan Sanan ’s official Weibo announced that their R&D office building was officially completed and opened !
In terms of project construction, the total investment in Hunan Sanan's silicon carbide semiconductor industrialization project is 16 billion yuan . In 2022, the investment will reach 3.636 billion yuan. As of 2022, the cumulative investment will reach 7.706 billion yuan. After the project is fully completed, the annual SiC production capacity will be Reaching 360,000 pieces .
According to the 2022 financial report, Hunan Sanan's silicon carbide production capacity has reached 12,000 pieces/month , and its silicon-based gallium nitride production capacity is 2,000 pieces/month . At present, the company's silicon carbide business is in a stage of smooth advancement.
Hunan Sanan's silicon carbide substrates have been verified by several major international customers, one of which has achieved batch shipments , and the supply in 2023 and 2024 has been basically locked.
I posted some articles and ideas myself here
I saw somewhere that someone proposed that the switch to titanium vs. stainless steel was to blame due to thermal conductivity differences, but this seems like rubbish as the heat transfer surface area of that band is tiny, and neither metal is a good heat sink (vs. something like copper or aluminum). While Apple's design choices are partially at fault, it would seem that they expected better performance from the TSMC process.
Samsung has been having similar overheating and yield problems with all their sub 10nm processes, affecting chips like Snapdragon 888, 8 Gen 1, and nVidia Ampere GPU (resulted in the loss of nVidia's business).
Intel's struggles with sub 10nm are well publicized.
With this in mind, if SMIC 7nm yield is decent, then actually they are not far behind at all.
Guangli Microelectronics releases CMPEXP modeling tool to enrich manufacturing EDA product matrix
Recently, in order to fill the gap in industrialized CMP modeling tools in the domestic integrated circuit market and meet the needs of chip design companies and wafer manufacturing plants, Guangli Microelectronics officially launched the CMP EXPLORER (referred to as " CMPEXP ") tool to ensure the manufacturability of chips. performance and yield, solving the pain points of the industry. Chemical Mechanical Planarization CMP is a key link in the integrated circuit manufacturing process. It combines chemical reaction and mechanical grinding to achieve a high degree of planarization of the silicon wafer surface.
With the evolution and iteration of integrated circuit manufacturing processes, the size of nano-devices continues to shrink. Coupled with the increasing level of integration and the increasing number of process levels, the surface flatness of chips at each stage of manufacturing seriously affects product yield and performance. Its impact is through The effect of multi-layer superposition and layout features is more prominent, which can be said to be "a slight difference is a thousand miles away". How to implement simulation, modeling and optimization of CMP steps has always been an important challenge to ensure chip yield.
Even if the design rules are strictly followed during chip design, for some process-sensitive design patterns, defects such as dishing, dielectric corrosion, and metal thickness fluctuations may still form during the CMP stage, resulting in interconnect failures. Line resistance, capacitance fluctuations, and even metal interconnect shorts and opens. As a result, the process window in subsequent manufacturing steps becomes narrower, and any small fluctuations in the process can cause yield problems. Therefore, the role of Design for Manufacturing DFM is more important. Through accurate simulation for the CMP step and modeling can identify and prevent CMP-related chip design issues in advance.
CMP: Chemical Mechanical Polishing.
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