Eh, I’m going to nitpick a bit more here and point out that you can’t get a clean power consumption and performance comparison simply out of density comparisons. The transistor design itself matters in parameters like voltage swing performance, drive current performance, current leakage, etc. and those are determined by more than feature size measurements.
Indeed, it's more complicated than just simple shrink to obtain the best Power & Performance. Feature size, capacitance, supply voltage, threshold voltage, Gate width, Gate length, etc. all contribute to Power. But in general, smaller feature sizes has a significant influence on the final performance & power consumption, smaller gate width lead to lower threshold voltage and thus lead to lower leakage and thus lower power cosumption.
more than happy to discuss everything in more detail, for example, on why tsmc actually relaxed M1 CD features relative to CPP going from 7nm to 7nm+. What I provided is a general comparison for general consumption for those not intimatly familiar with ins-and-outs of semiconductor design and fabrication.
With that said, actual PPA testing of 7nm, 7nm+, 5nm, 3nm do have the same correlation where the smaller nodes with smaller features have better PPACt performance. And since SMIC basically literally have suspiciously similar process to tsmc, you can assume if it has similar feature dimension it will perform relatively similar to the tsmc one.
Not sure what semiconductor segment you work in, but from a fab process capability standpoint, there is a freakin reason why we track CPP, MMP, cell area, etc.. It's like I said, a general first step of benchmarking that could be done purely
on paper. Then subsequent comparison would be to perform actual testing
on the actual chip to benchmark PP portion of PPACt. TechInsight does the exact same evaluation, so don't understand what your objection to this methodology is.
If you have data to show larger CPP, M2 transistor have better PPACt do share that data.. Better yet, since you object to the general benchmarking methodology I shared, why don't you show proof that SMIC N+2 with similar feature size to tsmc 7+nm could outperform tsmc 5nm with smaller features or if PPACt performance of nodes with larger featuers would outperform one with smaller featuers?
