Chinese semiconductor industry
- Thread starter Hendrik_2000
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No. Saw someone post an actual 60+ pro
Huawei: What Controversy?
What is funny is the Hynix and Micron memory chip inside the Mate 60 Pro. Apparently those two companies are forbidden to make sales to Huawei, by American law.
So Hynix and Micron claim innocence.
Ha!
They guilty!
Going to interesting the tear down of this phone because there will be more memory! More Hynix and more Micron, or will there be another mystery supplier?
Is there Micron in it? I don't think so. In all the teardown videos I have seen Storage and RAM chip are both from SK Hynix.
For those interested in analysis of technical data, please read on, otherwise you can skip this post.
I just read the latest TechInsight report on teardown of Kirin9000s. It looks like the chip is just a tad worse than I had thought. Many on social media had assumed this chip to be similar to tsmc 7nm+ with transistor density of 114ish MTx/mm^2. But the dimension on Kirin9000s with SMIC N+2 is a bit larger, so the cell area would be larger, and thus lower transistor density than tsmc 7+nm process..
Some critical dimensions measured and provided by TechInsight:
- Hi36A0 GFCV120 die size: 10.66 x 10.39 mm (110.8 mm^2)
- fin pitch: 33nm
- CPP: 63nm w/ SDB
- M2: 42nm
- Standard Cell height: 252nm (6-track)
How does this compared to N+1 & tsmc 7nm+?
I had previously indicated N+2 process would be better than tsmc 7nm but worse than tsmc 7nm+. But the Metal2 (M2) dimension on SMIC N+2 based on TechInsight's analysis is 5% larger than my assumption. The N+2 Contact Poly Pitch (CPP) is also 5% larger than my assumption. Taken CD sizes provided by TechInsight, the cell area would reduce and Transistor density increase by ~15% from N+1. So rough estimate, N+2 would have Trasistor density of ~104M Tx/mm^2 ish. Not exactly at tsmc 7nm+ level, but close enough.
Anyhow, this is comparison of SMIC's process capabilities in terms of PPACt on a transistor level. N+2 will be slightly inferior to tsmc 7nm+ in terms of Performance, Power consumption, Area, and perhaps cost. Slight improvements or differentiations could still be made through optimization of chip design (e.g. better designed chip with N+2/104 MT/mm^2 process may yield similar performance as a typical design on tsmc 7nm+/113.9 MT/mm^2). But fundamentally, you will not expect the N+2 to reach the level of tsmc 5nm which would have better PPACt due to smaller dimensions, higher transistor density, etc.
Note: all info except SMIC N+2 above could be found and verified on websites like wikichip.org; semiwiki.com, and even articles. info for N+2 I obtained through TechInsight's report.
I just read the latest TechInsight report on teardown of Kirin9000s. It looks like the chip is just a tad worse than I had thought. Many on social media had assumed this chip to be similar to tsmc 7nm+ with transistor density of 114ish MTx/mm^2. But the dimension on Kirin9000s with SMIC N+2 is a bit larger, so the cell area would be larger, and thus lower transistor density than tsmc 7+nm process..
Some critical dimensions measured and provided by TechInsight:
- Hi36A0 GFCV120 die size: 10.66 x 10.39 mm (110.8 mm^2)
- fin pitch: 33nm
- CPP: 63nm w/ SDB
- M2: 42nm
- Standard Cell height: 252nm (6-track)
How does this compared to N+1 & tsmc 7nm+?
| tsmc 7nm+ | SMIC N+2 | tsmc 7nm | N+1 | |
| fin pitch | 30nm | 33nm | 30nm | 37nm |
| CPP | 57nm w/ SDB | 63nm w/ SDB | 57nm w/ DDB | 63nm w/ SDB |
| M2 | 40nm | 42nm | 40nm | 44nm |
| cell height | 240nm | 252nm | 240nm | 264nm |
| M Tx/mm^2 | 113.9 | est. <104 | 96.5 | 89 |
I had previously indicated N+2 process would be better than tsmc 7nm but worse than tsmc 7nm+. But the Metal2 (M2) dimension on SMIC N+2 based on TechInsight's analysis is 5% larger than my assumption. The N+2 Contact Poly Pitch (CPP) is also 5% larger than my assumption. Taken CD sizes provided by TechInsight, the cell area would reduce and Transistor density increase by ~15% from N+1. So rough estimate, N+2 would have Trasistor density of ~104M Tx/mm^2 ish. Not exactly at tsmc 7nm+ level, but close enough.
Anyhow, this is comparison of SMIC's process capabilities in terms of PPACt on a transistor level. N+2 will be slightly inferior to tsmc 7nm+ in terms of Performance, Power consumption, Area, and perhaps cost. Slight improvements or differentiations could still be made through optimization of chip design (e.g. better designed chip with N+2/104 MT/mm^2 process may yield similar performance as a typical design on tsmc 7nm+/113.9 MT/mm^2). But fundamentally, you will not expect the N+2 to reach the level of tsmc 5nm which would have better PPACt due to smaller dimensions, higher transistor density, etc.
Note: all info except SMIC N+2 above could be found and verified on websites like wikichip.org; semiwiki.com, and even articles. info for N+2 I obtained through TechInsight's report.
But in their public blog post they said die size is 107 mm2
bro, you are nit picking. LOL
Die size of 107mm^2 is if measured only from die seal. Full die size would be 110.8mm^2.
"The Hi36A0 GFCV120 die is 10.50 mm × 10.23 mm (die seal) (107.4 mm2) as measured from the die seals, or 10.66 mm × 10.39 mm (110.8 mm2) for the full die"
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