Chinese semiconductor industry

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tphuang

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Moore Thread launches a new multi-functional domestic GPU product MTT S3000: MUSA architecture + PCIe 5.0 interface
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This is just brilliant, btw they also came out with S80 desktop GPU. S3000 looks to be a AI GPU
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This was quite the announcement and very impressive for a firm that was founded in Oct 2020. These are huge progress for 2 years. It really does help that the founder was previously Nvidia's global VP and head of China operation. If you look at the specs, their desktop GPU is so much better than that of Zhaoxin.
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Their S60 (from March) can do 6 TFLOPS of INT32 on 12 nm process (compared to just 1.5 TFLOPS from Zhaoxin)
and S2000 (server version) can do 12 TFLOPS of INT32

Even S60 was comparable to RTX 2060 in INT32 computation and was running league of nations. This new one has upped it to 14.4 TFLOPS and performance is supposed to have more memory, more cores and do more computation than RTX 3060. Although who really knows how things work out in practice. On top of that, it is apparently compatible with CUDA, whatever that means. Not sure how that works out since CUDA is a proprietary language. Maybe they support the most basically feature set of CUDA. Sounds quite impressive and works with a bunch of higher end games.

sales with start on Nov 11th. Quite impressive
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tphuang

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S3000 is a little bit of a tweener
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It has 220 billion transistors. 4096 MUSA cores + 128 dedicated computational core. It claims to be able to do 15.2 FP32 TFLOPS. Which is only slightly higher than S80. At least on the face of it, it seems to be not even at the level of Kunlun-2 chips from Baidu. Not looking to play in the very high end GPGPU market. Although, I guess if you stack enough of them together, it can be used in AI cloud also.

I think the most interesting part here is the compatibility with CUDA. Maybe that's something Biren tech can work on also. It's also compatible with Paddle Paddle, Pytorch and other AI languages. Looks like they generally just started out in the desktop GPU space and are moving to server/ai cloud secondly.

The other interesting part is the lack of announcement for the process or the maker. Based on transistor count, this looks like close to 7 nm process. It's quite possible this is based on SMIC's N+1 process.

On another note, it's quite impressive they can put a new generation product on the market in 7/8 months. If that's turnaround time for these new Chinese GPU chip designers, then I think Biren can put something out using SMIC process by early next year.
 

ansy1968

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We anticipate a drop BUT not this bad!!!! With weaker demand on its 7nm chips and the challenges from SMIC 14nm against their 16nm, only the 5nm is their major revenue generator as their savior the 3nm is having problem attracting customers due to high production cost.

TSMC Cuts Down Orders By Up to 50%, Sending Shockwaves Says Report​

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Nov 1, 2022, 03:11 PM EDT


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FILE PHOTO: The logo of Taiwan Semiconductor Manufacturing Co (TSMC) is pictured at its headquarters, in Hsinchu, Taiwan, Jan. 19, 2021. REUTERS/Ann Wang




This is not investment advice. The author has no position in any of the stocks mentioned. Wccftech.com has a
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The Taiwan Semiconductor Manufacturing Company (TSMC) has cut down its orders to suppliers according to reports in the Taiwanese press. TSMC, which is facing an industry slowdown as its customers struggle with demand slowdown, cut down capital expenditures for 2022 earlier this year, and the firm cited a lack of demand forecasting as the primary reason behind the drawdown. Now, the firm is also rumored to have significantly reduced its 3-nanometer output estimates for this year, in the latest bit of speculation surrounding the advanced chip manufacturing technology scheduled to enter production in the current quarter.

TSMC's 3-nanometer Average Monthly Production To Drop By 77% Says Report​

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comes courtesy of the United Daily News (UDN) and it speculates that TSMC has started to cut down its supplier orders. These orders form the backend, or upstream, of the semiconductor manufacturing supply chain, and they involve a variety of products such as TSMC procuring silicon wafers and other consumable to keep its machines running.
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UDN's sources believe that TSMC has reduced these orders by as much as 50%, with the drop coming after the fab also cut down its spending. Due to the critical nature of the company as Taiwan's largest and leading chipmaker, the order cutdown has also sent shockwaves down the chip sector as a whole.
TSMC, and the chip sector has also been facing inventory corrections this year, and the company expects these conditions to persist and potentially peak during the first quarter of next year. The chipmaker has however seen strong demand for its leading edge 3-nanometer technology, with its chief
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that the tape-outs for 3nm are more than double than the ones TSMC received for earlier technologies. In the chipmaking industry, tape-out refers to the finalized design from companies such as AMD which is sent to the chipmaker so that the latter can tailor its equipment to the product.

TSMC-THIRD-QUARTER-2022-REVENUE-BREAKDOWN

TSMC's third quarter of 2022 earnings report revealed that while revenue contribution from older technologies fell, its latest 5-nanometer products managed to grow. Image: TSMC
According to TSMC's suppliers, the order flow started to weaken in the previous quarter, and this has continued into the current quarter and into the first quarter of next year as well. TSMC shared during its latest earnings report that it is facing difficulty in procuring chipmaking equipment, especially to keep up with its customer orders, and that this when combined with an industry slowdown is forcing the firm to reduce spending.
On the topic of 3-nanometer, the picture painted by UDN is not great either. Its sources suggest that the monthly average output for the new technology was slated to sit at 44,000 wafers previously, and this has now dropped by a whopping 34,000 wafers to now sit at 10,000 wafers for a 77% drop. Key reasons behind this drop are reduced orders from both Apple and Intel - with Intel's own technology also facing delays and Apple choosing to launch its M2 personal computers in March. These imply that TSMC will not be making any chips for Apple this year, and since Intel itself is also facing delays, its products which use some of TSMC's chips will also see orders flow in later.
Today's report is the latest bit in a gloomy outlook for the chip sector, which was one of the best performing industries as earlier as last year as a massive influx of orders in the wake of the coronavirus pandemic and the auto industry led to more orders than the chipmakers could absorb.
 

tokenanalyst

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Zhengfan Technology: The cumulative orders in hand from January to September were 3.109 billion yuan, a year-on-year increase of 63.7%​


On the evening of November 3, Zhengfan Technology announced that the industry in which the company operates is developing rapidly, and the company's business has grown steadily. As of September 30, 2022, the company's orders in hand were 3.109 billion yuan, an increase over the same period last year. 63.7%. Among them: the orders in hand in the IC (integrated circuit) industry market were 1.481 billion yuan, an increase of 97.8% over the same period of the previous year; the orders in hand in the photovoltaic industry market were 721 million yuan, an increase of 80.4% over the same period last year; The order in hand is 907 million yuan.

Previously, Zhengfan Technology said that usually the orders in hand at the end of the third quarter will be slightly higher than that in the second quarter. However, due to the impact of the epidemic in the second quarter of this year, the progress of order delivery and revenue recognition has slowed down. The data of revenue recognition in the third quarter is a result of our accelerated catch-up, so the contracts in hand in the third quarter will be different from previous years.

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gelgoog

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I was looking at Innosilicon's IP blocks page and some of them use the following SMIC processes:
- 14SF+
- 14SFE
- 8/10SF+
- 8/10SFE
- 7

So these should be the processes SMIC has for 14nm, N+1, and N+2.
It seems like 14nm and N+1 (8/10nm) have specific power optimized and performance optimized processes.
 

tokenanalyst

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Important progress has been made in the direction of efficient federated learning for IoT applications where microelectronics is located​

Source of the manuscript: Guo Ye, EDA Center Release time: 2022-11-02
Industrial Internet of Things, including the development of EDA tools for wafer manufacturing in semiconductor manufacturing, involves a large number of process and equipment parameters. How to effectively use machine learning to perform accurate process simulation on the premise of ensuring the sensitive parameters of the enterprise is the current core technical difficulty. Federated learning allows multiple participants to train deep learning models in a distributed and collaborative manner without disclosing the original training samples, which can provide algorithm guarantees for privacy-sensitive, IP -protected smart IoT applications. But in a traditional federated learning framework, the client needs to perform multiple rounds of intensive computation including forward and backpropagation, which is likely to exceed the upper limit allowed by typical IoT endpoints in terms of computing performance, energy, and storage capacity. Frequent communication between server and client is also easy to become a bottleneck restricting system performance. The industry urgently needs a more efficient federated learning framework to enable the deployment of this privacy-preserving scheme in Internet of Things ( IoT ) systems.
  Recently, the team of researcher Chen Lan from the Institute of Microelectronics proposed a computational and communication-efficient federated learning framework "FedQNN" ( Figure 1 ) for IoT applications. For the first time, ultra-low bit-width quantization technology was integrated into federated learning, allowing the client Performing the vast majority of the computational load in a lightweight fixed-point format greatly reduces computational power consumption ( Fig. 2 , a ). In terms of communication, this framework utilizes sparse and quantization strategies to compress upstream and downstream data. The experimental results on multiple data sets and models show that this framework can reduce the terminal computing energy consumption by 90% , compress the model size by more than 30 times, and greatly reduce the communication bandwidth without significantly affecting the model accuracy. demand and the amount of transmitted data ( Fig. 2 , b ), significantly reduce the deployment cost of federated learning, improve its utility in IoT systems, and provide a new approach to address data privacy protection in the field of smart wafer fabrication EDA tools .




W020221102520998871986.png


Figure 1. System framework diagram of FedQNN algorithm

W020221102520999003082.png


Figure 2. Learning curve graph under different datasets

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theorlonator

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Thanks, very interesting video. I wonder what all the knowledgeable contributors in this thread think about the answer given by Paul Triolo to the general question on whether China is doing the right thing with respect to the US chip sanctions. The question is here:
His answer is bad. He is overlooking how Chinese equipment providers are doing and that Chris guy said to essentially "buy more American equipment." This isn't a foreign policy thread, but freezing your defense spending and output to hope the US government will allow you to what? But an EUV machine? Like that was ever on the table anyway.
 

tphuang

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I was looking at Innosilicon's IP blocks page and some of them use the following SMIC processes:
- 14SF+
- 14SFE
- 8/10SF+
- 8/10SFE
- 7

So these should be the processes SMIC has for 14nm, N+1, and N+2.
It seems like 14nm and N+1 (8/10nm) have specific power optimized and performance optimized processes.
Bro, where are you seeing this? Can you provide a link? I wouldn't be surprised if they are already producing n+2 for small mining chips.
 
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