Chinese semiconductor industry

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hvpc

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BYD Reaches Cooperation With Local Chip Startup Horizon Robotics.​

Shenzhen-based electric vehicle maker
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, which will provide its self-driving “Journey 5” computer chip for certain BYD models set to be launched next year, significantly enhancing their autonomous driving capabilities.

BYD models equipped with the Journey 5 chip will be available by mid-2023 at the earliest. This partnership marks a breakthrough in actual business cooperation between the two companies following BYD’s investment in Horizon, with BYD becoming the first car company to announce it will use the Journey 5 chip in its vehicles. The two companies will deepen their cooperation in the future, and Horizon Robotics’ Journey series chips will be available across a wider range of BYD models.

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@tokenanalyst , any idea who makes Horizon Robotic's chips? Could it be SMIC's N+1 process? This would be good news for SMIC.
 

hvpc

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Well, there are many no-solder wafer bonding methods, one coming to mind being YMTC Xtacking. I do not know the details for the Huawei particular process.
I'm only aware of hybrid bonding for advanced packaging, which is based on van Der Waal force to hold two chips together. This is what tsmc is looking into for their future advanced packaging needs.

Xtacking is a YMTC marketing term. If I remember correctly they use wafer to wafer fusion or hybrid bonding.
 

FairAndUnbiased

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I'm only aware of hybrid bonding for advanced packaging, which is based on van Der Waal force to hold two chips together. This is what tsmc is looking into for their future advanced packaging needs.

Xtacking is a YMTC marketing term. If I remember correctly they use wafer to wafer fusion or hybrid bonding.
It is a copper to copper bond at the bond pad.

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tokenanalyst

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@tokenanalyst , any idea who makes Horizon Robotic's chips? Could it be SMIC's N+1 process? This would be good news for SMIC.
The report don't say the node size. But it could be. Chinese AI companies are starting to use Advance packaging techniques to get more performance out their solutions using mature nodes.

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Alibaba Dharma Institute successfully developed an AI chip with integrated storage and computing: using hybrid bonding 3D stacking technology​

China's flash memory market 2021-12-04 00:40:10 6

Alibaba Dharma Institute's storage and computing integrated AI chip hybrid bonding 3D stacking technology

Alibaba Dharma Academy recently announced that it has successfully developed an artificial intelligence (AI) chip that integrates storage and computing.



Real shot of the integrated chip of Dharma Institute, source: public information

According to the Bodhidharma Institute, the integrated storage and computing chip integrates a number of innovative technologies, and is the first chip in the world to use "hybrid bonding 3D stacking technology" to achieve integrated storage and computing. The birth of this new architecture chip is expected to help the storage and computing integration technology move from concept to implementation, and is expected to be widely used in VR/AR, unmanned driving, astronomical data computing, remote sensing image data analysis and other scenarios in the future.

The data shows that the integrated storage and computing chip is similar to the human brain. By integrating the data storage unit and the computing unit, the transmission and handling of data can be greatly reduced, thereby greatly improving the parallelism and energy efficiency of computing. However, although the memory-computing integrated technology was proposed as early as the 1990s, due to the complexity of the technology, high design costs and lack of application scenarios, the industry has made research progress on memory-computing integrated chips in the past few decades. slow.
 

hvpc

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The report don't say the node size. But it could be. Chinese AI companies are starting to use Advance packaging techniques to get more performance out their solutions using mature nodes.

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Very nice that they were able to make this work. I wonder if this is production ready with acceptable yield? It also look like they use foreign HBM since no one in China could do D1y yet.

this paper talked about using 3D boding (hybrid bonding) that is same as YMTC Xstacking as well as using 2.5D packaging (TSV) to stack HBM (high bandwidth memory). For those interested about various methods used in HITOC from interposer, TSV, to hybrid bonding, this paper may be a good read.

The paper's conclusion is of no surprise. One important thing this paper din't touched on is the cost; the extra cost from yield loss and the extra cost with the extra manufacturing steps and integration steps. Using HITOC w/ less advanced chips to achieve performance of more advanced chip is no surprise. The biggest reason why industry stuck with 2D shrink is the is still cheaper. But with 2D shrinking hitting a wall soon, heterogeneous integration will definitely become more main stream. I think this will start to happen as soon as 2nm node comes around. But because China have no access to advanced chips, it will be forced to go with this more expensive option sooner (at older logic/dram nodes) than rest of the world.
 

antiterror13

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Yeah. I was responding to "bleak". it's definitely not an appropriate adjective.

I think SMIC definitely has chance to catchup per your assessment. But in order for that to happen they need to outspend and out innovate tsmc. I'm not too please to see SMIC is only planning to invest $5B in Capex this year; not much of a difference from last year..and the RD expense is decreasing because of "slower RD activities". Many of us are cheering on SMiC, but their current plan is definitely not meeting our expectations.

tsmc plans to spend $44B this year; actual spending by year end may be even higher.

We need SMIC to spend more! I see SMIC surpassing GF and UMC in a few years, but it need to have more output in 28nm & below. Based on its financial report, its shipping only ~30K wafers/month of 28nm & below. SMIC needs to gain a bigger share of the advance nodes, period. Do you know SMIC's current share (5.3%) of foundry business is lower than what they had in 2006 (6.8%)? Unless SMIC master 7nm soon, the gap with tsmc will only get bigger. 28nm wafers costs $3000, 3nm wafers costs more than $15,000. And in a year tsmc will have more wafer output than smic 28/14/7nm. So, you see, SMIC can't challenge tsmc until it spends more $ and produce more profitable advanced wafers. It seems SMIC is focused on making money in the old nodes and not focusing on trying to catch tsmc.

By the way, regarding Japan, they do have advanced fabs. They don't have advanced logic fabs, but they do have leading edge memory fabs. Micron and Koxia are currently producing more advanced DRAM and 3D-NAND than CXMT & YMTC.

I agree to all of your items there. I thing the reason SMIC spending is not spectacular, because SMIC is waiting for local lithography machine become available ... there is no point spending huge capital and then get sanctioned by the bully, and the bigger SMIC is the more chance will get sanctioned. I think the important point is in 2023 - 2025 when local Chinese lithography manufacturers (SMEE, etc) may finally able to produce reliable high end DUV equivalent to ASML 2050i with perhaps 1/2 price, at that point I believe SMIC and others will invest hugely. There is a chance that China may break EUV litho in 2026-27, could be revolutionary with SSMB

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hvpc

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I agree to all of your items there. I thing the reason SMIC spending is not spectacular, because SMIC is waiting for local lithography machine become available ... there is no point spending huge capital and then get sanctioned by the bully, and the bigger SMIC is the more chance will get sanctioned. I think the important point is in 2023 - 2025 when local Chinese lithography manufacturers (SMEE, etc) may finally able to produce reliable high end DUV equivalent to ASML 2050i with perhaps 1/2 price, at that point I believe SMIC and others will invest hugely. There is a chance that China may break EUV litho in 2026-27, could be revolutionary with SSMB

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Well, I think everyone on this forum would certainly hope so.

Since I'm closer to the industry than most of you, I'm a bit more skeptical based on what I'm see and hear. But, I'd love if I' proven wrong. : )

How old is the info in the link you provided? I'm surprised at these two statements as it seems to differ from what was shared I this forum recently:

"A completely operational SSMB source has still to be demonstrated."

"If funding is forthcoming, the Tsinghua team hope to construct a dedicated SSMB storage ring in Beijing, says Tang.“If things go well, we plan to build it in the following five to six years.”"

What's your interpretation/take on this?
 

hvpc

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Yes, there's also silicon to silicon direct wafer bonding, as well as silicon-metal-silicon, and dielectric-dielectric.
maybe I mislead you. hybrid bonding today is mostly between silicon/silicon wafers, but the bonding pad material is copper.

I'm not following/understanding the "types" of wafer bonding you mentioned. Could it be that we are talking about the same thing but using different terminology?? everything you listed, I'm just calling Hybrid Bonding.

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