Chinese semiconductor industry
- Thread starter Hendrik_2000
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The Chinese equipment manufacturers have equipment variosuly at 28/14/7/5nm nodes. They're not as good as the foreign ones; that's why they don't have much market share since Chinese fabs don't want to take too much risk. Now the fabs and equipment makers are in the same boat. They need to work together. The equipment makers got more market share and opportunities. They will iterate their product development more quickly. Majority of the demands are 20nm and above, so they don't need to work on the 5nm node right out of the gate.
This dynamics is not too complex to understand. It doesn't take a genius.
This dynamics is not too complex to understand. It doesn't take a genius.
Chinese self-sufficiency at intel equivalent 10nm would actually imply that other Fab equipment in the supply chain are also close to state of the art.
Even if China doesn't get to 5nm or 3nm to compete for the phone/pc end-user, it would still be able to capture a significant amount of equipment market on the international stage.
Most of the fabricated chips on the market are >14nm
If Chinese companies can dominate the DUV market, then it will have sufficient profit to research further and compete in the next generation.
Most companies don't need EUV products mainly due to cost.
Even if China doesn't get to 5nm or 3nm to compete for the phone/pc end-user, it would still be able to capture a significant amount of equipment market on the international stage.
Most of the fabricated chips on the market are >14nm
If Chinese companies can dominate the DUV market, then it will have sufficient profit to research further and compete in the next generation.
Most companies don't need EUV products mainly due to cost.
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manqiangrexue
Brigadier
So either you haven't been reading this thread thoroughly and only came to ask stupid questions to try to poopoo the situation or you are selectively failing to read what you don't want to be true. It was mentioned here many times that the SMEE DUV is set to be completed in 2021 and the EUV has had all of its components ready but needs assembly and integration, with an estimate of 2022. Dig through the forum; don't ask to be spoon-fed everything.
I'm sorry but your poor reading comprehension does not excuse you from the need to understand the content. It doesn't matter how old I am if you're not old enough to master basic reading comprehension, you know. This post explained why it is a stupid question; you need to read for understanding, not confirmation of your hopes.
From 1,015 (Chinese semiconductor industry)
"You're very impatient. Why would you ask that question now if you know it's at least a year and a half before there needs to be answer? If China and Huawei are working on many projects in lithography, most of which aren't scheduled to have results until 2021-2022, where would you possibly expect an answer to come from at this time? Even the engineers themselves are still working on the solution so where on this forum would you expect to find someone who not only knows classified information, but also can see into the future?
The question shouldn't even be mentioned until at least a year later when some of the projects are expected to yield fruit. By that time, you may not need to ask. As of now, that question is as impatient as it is stupid. "
If anything I think those charts might be underestimating the Chinese industry. Counting revenues in US Dollars instead of wafers or valid chips or whatever is kind of disingenuous. The equipment, also by revenue, well it is obvious that Chinese companies do not have leading edge equipment often or need to break into the market so, yes, of course the revenues will be lower.
If we are talking about fabrication I think the only metric that matters is wafers per month or per year of a given node. Thing is this information is seldom made public because it basically tells your opponent what your operating margin is. At best they give you peak theoretical wafers per month or whatever.
If we are talking about fabrication I think the only metric that matters is wafers per month or per year of a given node. Thing is this information is seldom made public because it basically tells your opponent what your operating margin is. At best they give you peak theoretical wafers per month or whatever.
AssassinsMace
Lieutenant General
All you need to know is the most advanced US nuclear warhead was designed on an Apple IIe.
A very good summary from FairAndUnbiased (Pakistan Defense Forum)
As you may have read in an earlier article, the new trend is 3D usage of wafer space instead of planar structures or 2.5D single layer structures. This is because EUV is very expensive, there is a supplier monopoly, and it seems to be hitting both physical and performance limits. Even US companies like Global Foundries gave up on it. So, let's look at 3D wafer fabrication. Here, Chinese fabs are innovators and for memory applications
In this situation, one type of wafer structure - such as 3D NAND structures - are fabricated on a separate wafer than another - logic and readout circuits. You then physically bond them together with wafer-wafer bonding techniques. This means that you no longer waste half your space: you have logic circuits stacked on your memory circuits, doubling the die area dedicated to memory, instead of wastefully putting them side by side. Imagine this applied to other logic circuits. This is the 3D integration that makes the entire EUV paradigm questionable from both cost and performance point of view, and it's already a commercial product. Imagine the possibilities.
The real question is actually much more complex. TSMC has gone all in on EUV. They collaborated with ASML. They want the smallest line width resolution possible. So far, much EUV work (down to even 7 nm nodes) can actually be replicated by traditional DUV immersion lithography that just double patterns. However at <7 nm nodes they need EUV lithography. Note that the line widths aren't literally 7 nm, they are just a 'performance equivalent' or 'density equivalent'.
As you may have read in an earlier article, the new trend is 3D usage of wafer space instead of planar structures or 2.5D single layer structures. This is because EUV is very expensive, there is a supplier monopoly, and it seems to be hitting both physical and performance limits. Even US companies like Global Foundries gave up on it. So, let's look at 3D wafer fabrication. Here, Chinese fabs are innovators and for memory applications
In this situation, one type of wafer structure - such as 3D NAND structures - are fabricated on a separate wafer than another - logic and readout circuits. You then physically bond them together with wafer-wafer bonding techniques. This means that you no longer waste half your space: you have logic circuits stacked on your memory circuits, doubling the die area dedicated to memory, instead of wastefully putting them side by side. Imagine this applied to other logic circuits. This is the 3D integration that makes the entire EUV paradigm questionable from both cost and performance point of view, and it's already a commercial product. Imagine the possibilities.
Except, your compute to power ratio (aka your power efficiency) is still dependent on your process node. You can sandwich more transistors into an area but it doesn’t make a larger node 3D stacked chip as efficient as a smaller node. Insofar as performance goes, we’ve more or less hit diminishing returns on chip size. Efficiency matters more.
The Chinese system depends a large part on market forces with a helping hand or guardian from the government. So yes, the Chinese will buy the best the market can offer on price and quality. But due to the sanctions by the US, the Chinese have no choice except to buy local and innovate. That is why a lot of plans, breakthroughs and achievements were being announced lately.
The future is looking good. They seem to be confident in what they are doing. The on going pandemic is giving them more time and a better economy in relation to other countries, giving them at least two years lifeline.
It seems to me that you have run out of arguments and want to bail out of the discussion. If so, i understand.
Its easy to argue in this way. Saying something and not backing it up with sources, and then tell the other to go search for it. Perhabs what you say is right, but i want to see the information sources.
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