Chinese semiconductor thread II
- Thread starter vincent
- Start date
The statement from Tongji University President.
In May 2025, the team delivered its first ArF immersion lithography machine to SMIC. With the help of multiple exposure processes, it can stably support the production of chips with a process of 7nm and above, breaking the long-term monopoly of foreign countries in the field of high-end front-end lithography equipment and achieving a historic leap in the research and development and manufacturing of high-end lithography machines in my country.
江丰电子 reports delivery of high purity 6N silicon target for advanced memory chip production. Claims to be the only one to do it globally outside of Japan's JX and US' Honeywell. It also has advanced high purity Tungsten targets for memory chip production. And 30mmcopper Manganese target.
It has major expansion project in Korea (next to Samsung & SK) as well as Shejiang Haining.
my summary on this, it seems like China has the fully supply chain now that's very low cost for optical transceivers.
According to SemiAnalysis teardown, SMIC N+3 has a Transistor Density of 113.4MTr/mm2
SMIC N+3 and TSMC N6’s HD library both feature a CGP of 57 nm. For SMIC, this is a 9.5% shrink over N+2.
In the past, CGP and cell height alone may have been enough to compare transistor density. Now, however, we must consider scaling boosters and DTCO as well. SMIC’s density gain does not come from EUV. It comes from using every available DTCO booster aggressively.
First is fin depopulation: reducing the number of NMOS and PMOS fins in each cell. The first FinFET nodes started with 3 or 4 fins for each transistor. SMIC N+3 and TSMC N6 HD both use only 2 fins per transistor, trading drive strength for density.
Next is contact over active gate (COAG). By landing the gate contact directly over the active gate, instead of out over the isolation region, the cell height drops. N+3 integrates COAG while N6 does not. Our N+3 gate-cut cross-sections indicate COAG, with the gate contact sitting over the active region, while N6 shows an off-gate contact.
Last is single diffusion break (SDB). Diffusion breaks are inserted between cells in the same row to provide electrical isolation, but they also introduce local layout effects (LLE), layout-dependent shifts in electrical characteristics. In the past, a double diffusion break was used, consuming the space of two CGPs. SMIC N+3 and TSMC N6 instead use SDB, saving area but increasing LLE sensitivity. This must be controlled at the process level and accurately modeled in the process design kit (PDK) so that EDA tools can account for it.
Overall, SMIC N+3 has a transistor density of 113.4 MTr/mm², slightly above TSMC N6 at 107.7 MTr/mm². Even without EUV, SMIC has achieved density beyond TSMC’s mature N6 node which utilizes EUV.
Last edited:
Seems like they deleted the paragraph.
from article.
theoretically SMIC could reach both N+4 and N+5 with DUV. we estimate that SMIC N+4 could reach a cell height of 198 nm and a CGP of 54 nm, implying a Bohr density of 137.8 MTr/mm², on par with TSMC N5 or Samsung SF4.
with , moving power routing and source/drain contacts to the backside, which would reduce front-side routing pressure and enable another reduction in cell height.This approach would allow N+5’s cell height to fall to 170 nm and its CGP to 53 nm. This implies a Bohr density of 163.6 MTr/mm².
------------------------------------------------------------------------------------
this is likely to be the last traditional chip from Huawei. This Kirin 9030 does not use LogicFolding, remaining in a conventional mobile SoC package. Future teardowns of Kirin and Ascend chips will show both planar logic density and Huawei’s hybrid bonding solutions. Kirin 2026 and Kirin 2027 chips both used LogicFolding.
teardown will be interesting for next Huawei chip.