ASML tested 500 watt light source in 2020. First EUV will be equivalent to 3400. Can't jump steps. NXE:3800E is for 2nm production. Unless SMIC jumps straight to 2nm I don't see it how it directly matches ASML.
Chinese semiconductor thread II
- Thread starter vincent
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Outside perhaps some optics refinements (and I’m only guessing there might be any here) the resolution of the 3800E and 3400C are exactly the same. 3800E is only dedicated for 2 nm insofar as 2 nm requires more patterning steps which means you need a faster instrument, which you achieve by increasing dosage rate, which you get via the higher power light source. Any wafer processing speed gain you get with a more powerful light source can be used for larger nodes too.
Zhenqu Technology completes E round of financing to accelerate mass production of new generation power modules
On February 28, Zhenqu Technology (Shanghai) Co., Ltd. (Zhenqu Technology) announced the completion of its E round of financing, led by SDIC, followed by Liuzhou 125 Industry Fund and Chongqing Liangjiang Fund. The financing funds will be mainly used to accelerate the mass production of new generation power modules, power bricks and electronic control products, promote the delivery of overseas customer projects, and further improve the domestic business layout and global market expansion
On February 28, Zhenqu Technology (Shanghai) Co., Ltd. (Zhenqu Technology) announced the completion of its E round of financing, led by SDIC, followed by Liuzhou 125 Industry Fund and Chongqing Liangjiang Fund. The financing funds will be mainly used to accelerate the mass production of new generation power modules, power bricks and electronic control products, promote the delivery of overseas customer projects, and further improve the domestic business layout and global market expansion
7nm, and probably 5nm though I have a few doubts and that's it because 3nm for sure had EUV double patterning.
Urepu received a new round of financing, a semiconductor equipment company
According to the Hefei Investment Fund Association, recently, Unipu Semiconductor Equipment Co., Ltd. (hereinafter referred to as "Uripu") announced the successful completion of a new round of financing, which was exclusively invested by Hefei Industrial Investment Capital.
Founded in September 2021, URP is a company focusing on the research and development of semiconductor front-end measurement equipment. Its headquarters is located in Zhangjiang High-tech Park, Pudong New Area, Shanghai. It also has a research and development center in Jinqiao, Pudong, and a technology center in Wuxi High-tech Zone. The company's founder, Yu Xianyu, graduated from Wuhan University of Science and Technology, and later received a master's degree in microelectronics and solid-state electronics from Shanghai Jiaotong University. He has a rich and profound resume in the semiconductor industry. From 2006 to 2009, he worked as a global technical support engineer at Applied Materials in the United States (PDC headquarters in Israel), accumulating international cutting-edge technology experience; from 2010 to 2021, he served as the marketing director of Ruili Scientific Instruments (Shanghai) Co., Ltd., and has accurate insight into market operations and rich practical experience. 15 years of deep cultivation in the industry has laid a solid foundation for the establishment and development of URP.
It is reported that the FTIR equipment Eos200Lite produced by Urepu has received orders from many leading silicon carbide-based epitaxial plants. It is mainly used to measure the thickness and uniformity of the epitaxial layer of epitaxial wafers. At the same time, equipment such as Eos200/200+ and Eos300/300+ have also received numerous orders.
Don't focus too much in the light source, for now, is important, because is the part that determine the performance of the machines and Chinese institutions are looking into multiple types of light sources. But the resolution is all about the optics.
Resolution is irrelevant. EUV was a decade late so milti patterning is unavoidable. Some EUV double patterning can be replaced by DUV multi patterning as there are a few new tricks. Directed self assembly can be used to correct EUV patterns. Main pressing issues right now is mask performance and resist stochastics. I would also say that DPP is the final light source, maybe CO2 lasers can be replaced with DPSSL but this is the last light source. Lithography will hit a wall and further scaling will be achieved with new materials. As of now DRAM is about to hit the scaling wall and there are a ton of options for further scaling. VTFET, 4f2, IGZO and some other options. Logic will look at stacked transistors which is cfet followed by stacked logic and followed by true 3D logic.
