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Chinese semiconductor thread II
- Thread starter vincent
- Start date
The T1-2025 Memory_DRAM Briefing Video is new in the TechInsights Platform. The T1-2025 DRAM Analyst Briefing provides DRAM technology details, roadmap updates, trends, comparisons, and outlooks.
In this quarter (Q1 2025), a small portion of D1c will be revealed in the market, first from SK hynix. The D1c generation will be especially dominant in 2026 and 2027 including the HBM4 DRAM application. From a market view, HBM products, in particular HBM3 and HBM3E, currently show a high price and high performance, while legacy products such as LPDDR5 and DDR5 devices show a lower price and relatively lower performance. Industry DRAM wafer production is projected to grow 96% from 2023 to 2029. CXMT currently produces 170,000 wafers per minute (wpm), including its Hefei A2 fab, and it plans to extend to 190,000 wpm by the end of this year. This will grow to 220,000 wpm next year with the new Beijing Fab1, and a further 320,000 wpm in 2027 with the next Beijing Fab2. Therefore, CXMT wafer production is projected to be almost the same as Micron and SK hynix in five years.
DRAM foundries are eager to extend this by developing more innovative technologies, materials, and methodologies such as gate work-function engineering, HKMG, sensing margin and speed improvement, row-hammer scaling, higher-k capacitor dielectric materials, higher NA EUV tools, etc. For many years, innovative technologies have been adopted for each generation, such as dual WF buried WL, quasi-pillar one-sided capacitor structure integration, NbO dielectric layer, recess channel BL S/A transistors, HKMG peripheral DRAM transistor structure, EUV lithography, TiN-only WL, and 3-MESH structure. With these technology innovations, Samsung, SK hynix, and Micron scaled the D1b cell size down to 1.23K–1.33K nm2.
Higher memory capacity per die, for example, 32 Gb, 48 Gb, or 64 Gb dies, will be needed for future AI and datacenters; however, the 16 Gb die is still the mainstream in the current market. In higher-density DRAM chips, 3D DRAM architectures such as 4F2 vertical channel transistor (VCT) cells, IGZO DRAM cells, or 3D stacked DRAM cells should be developed and productized for the sub-10 nm class nodes (single-digit nodes), especially from the three big DRAM players: Samsung, SK hynix, and Micron.
Samsung and SK hynix currently lead the EUV lithography technology on DRAM devices, while the upcoming 1γ DRAM generation will be the first EUVL-applied device developed by Hiroshima R&D in Japan from Micron. D1c and D1-gamma generations will be an 11nm-class technology node. Before jumping into the single-digit node D0a, one more generation such as D1d may be added with 10nm D/R. Taiwan DRAM companies Nanya, Winbond, and PowerChip still have 30nm- and 20nm-class and higher 10nm-class DRAM products in the market such as 1A and 1B tech nodes from Nanya. CXMT in China released G3 generation DDR3L and LPDDR4X, it recently released LPDDR5 DRAM chips, and now it has G4 generation DDR5 and is developing a G5 generation.
D1a and D1b are the mainstream in the market. By the end of 2027, we expect DRAM will jump into the single-digit nanometer technology nodes such as D0a, and 0b and 0c generations will then follow. In the meantime, 4F2 and 3D DRAM prototypes will be developed for the next DRAM scaling candidates from major players such as Samsung, SK hynix, and Micron. For more details, please refer to TechInsights’ DRAM Technology Roadmap.
Surely they mean wafers per month?