Chinese semiconductor thread II

tokenanalyst

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Additive-Assisted Forming High-Quality Thin Films of Sn–Oxo Cluster for Nanopatterning​

Abstract​


Recently, metal–oxo clusters (MOCs) have attracted significant interest in fabricating nanoscale patterns in semiconductors via lithography. However, many MOCs are highly crystalline, making it difficult for them to form films and hindering subsequent nanopatterning processes. In this study, we developed a novel and simple method to enhance the film-forming ability of aromatic tetranuclear Sn–oxo clusters by adding additives. Theoretical calculations and Fourier-transform infrared (FTIR) analysis revealed the formation of intermolecular hydrogen bonds between the Sn–oxo clusters and additives, which induced a crystal–gel phase transition at −20 °C, thereby inhibiting the easy crystallization of the Sn–oxo clusters. High-quality and uniform thin films with surface roughness below 0.3 nm were prepared via spin coating. The obtained thin films exhibited good lithographic performance under deep ultraviolet (DUV), electron beam, and extreme-ultraviolet irradiation without a photo acid generator/photoinitiator, and 13- and 21 nm-wide line patterns were obtained on the films via electron-beam and extreme-ultraviolet lithographies. This study will pave the way for the further investigation of novel MOCs for advanced lithography and other thin-film applications.​

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tphuang

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CETC has developed MEMS pressure sensor using Cavity-SOI principle.

A special type of MEMS pressure sensor that can check tire pressure

150 kPa and 700 kPa MEMS sensors by 58th Institute can be applied for various purposes. It's working to have full coverage and mass production of 100 to 2000 kPa pressure sensors.
 

Clark Gap

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bottom 2 are from the more trustworthy source. But obviously some people are calling the process used on 9100 a 5nm process, but it's not a real 5nm process like N5, that's why the quote around it.

The key here is a frame interpolation technology for high load game rendering. This tech allows games to be run smoother with lower latency and power consumption.

Remember that the key problem with 9000S and 9010 is the high end gaming performance. That's the main issue being addressed in 9100.

I have discussed this with some Huawei employees, and they mentioned that Huawei has issued some chip samples with 140 MTR/mm^2 as souvenirs. As for the Mate 70's SoC, the internal company forum claims that it 'reaches the level of TSMC 5nm and has the performance of 8g2.'
 

tphuang

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I have discussed this with some Huawei employees, and they mentioned that Huawei has issued some chip samples with 140 MTR/mm^2 as souvenirs. As for the Mate 70's SoC, the internal company forum claims that it 'reaches the level of TSMC 5nm and has the performance of 8g2.'
these are strange claims.
"reaches the level of TSMC 5nm and has the performance of 8g2" doesn't mean anything.
things that matter are the critical dimensions. And 9000S critical dimensions are so far off N5 that it would be ridiculous to think they can make that jump in 1 improvement.

Could they have chip samples with 140 MMTR/mm2? Sure, but I don't think that's the process for 9100. You'd need a steady production process able to reliably produce 110mm2 die.
 
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