Chinese semiconductor thread II
- Thread starter vincent
- Start date
Basically nothing. They might forbid you from using the trademark and logo. But that would require them to convince Switzerland or the people in control of the foundation to do it. The only real problem is any hardware patents that exist which were created in the US or the West in general. I know that SiFive has a patent on fusion of branches in RISC-V CPUs for example. This patent wouldn't forbid you from making a RISC-V compatible processor but not having a license might mean you cannot implement certain features in the same way.
I did try convincing the guy choosing the license for the RISC-V architecture to base it on the Apache 2.0 License.
But they had to select the BSD one as the base... The faculty teachers always meant to create a business around the architecture.
I did try convincing the guy choosing the license for the RISC-V architecture to base it on the Apache 2.0 License.
But they had to select the BSD one as the base... The faculty teachers always meant to create a business around the architecture.
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took a look at Geekerwan review of Kirin-9010
They really changed so much in the big core. It's not 8-wide decode vs 6-wide. L1D TBL got larger, both integer and floating section got larger. level 3 cache got bigger. branch prediction miss rate got better.
It's a pretty good first step to their future sever CPU core
They are investing more money than anyone outside of ARM and Apple on core designs of ARM ISA. They are committed to it.
They really changed so much in the big core. It's not 8-wide decode vs 6-wide. L1D TBL got larger, both integer and floating section got larger. level 3 cache got bigger. branch prediction miss rate got better.
It's a pretty good first step to their future sever CPU core
They are investing more money than anyone outside of ARM and Apple on core designs of ARM ISA. They are committed to it.
I watched the video.
The new processor also seems to have one less pipeline stage. This should reduce the mispredicted branch penalty.
It runs at lower clockspeed. This probably makes it more energy efficient. It might run at lower temperature. I say might because it is wider overall at 8-wide vs 6-wide.
The new processor also seems to have one less pipeline stage. This should reduce the mispredicted branch penalty.
It runs at lower clockspeed. This probably makes it more energy efficient. It might run at lower temperature. I say might because it is wider overall at 8-wide vs 6-wide.
I dont know a lot about SoC or CPU, but Wouldn't a lower clock speed make it go slower?
It is 8-wide vs the older 6-wide core.
In engine terms. It is basically like the difference between an 8 cylinder and a 6 cylinder engine. The clockspeed is just the RPMs.
Performance = Clockspeed x IPC
An 8-wide processor has more IPC (Instructions Per Clock).
In engine terms. It is basically like the difference between an 8 cylinder and a 6 cylinder engine. The clockspeed is just the RPMs.
Performance = Clockspeed x IPC
An 8-wide processor has more IPC (Instructions Per Clock).
Lower clock but higher IPC (instructions per cycle).
Thanks. That's actually a really good analogy.