Chinese semiconductor thread II
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High-performance 4H-SiC EUV Photodiode with Lateral p-n Junction Fabricated by Selective-area Ion Implantation.
Abstract:
In this work, a 4H-SiC EUV photodiode (PD) with lateral p-n junction formed by selective-area ion implantation is investigated, in which grid-shaped p-type contact region is designed for enhancing effective EUV light absorption. The large area SiC PD with 9 mm diameter exhibits a low dark current density of ~9 pA/cm 2 and a high responsivity of 0.07 A/W at 13.5 nm under 5 V reverse bias. The detectivity of PD is further determined to be ~5.9×10 12 cmHz 0.5 W -1 based on 1/f noise test. Two-dimensional photocurrent mapping of photosensitive area indicates that the non-uniformity of photo-responsivity at 13.5 nm is less than 0.67%. When tested by using a 266 nm pulse laser, the PD shows a fast rise time of ~4.3 ns in transient response measurement. The PD also exhibits low dark current, stable capacitance and responsivity at elevated temperatures up to 150 °C, suggesting that the detector has good potential for high-temperature operation.
North Huachuang’s 12-inch TSV etching machine PSE V300 has been recognized by the market
In recent years, artificial intelligence has developed rapidly. 2.5D and 3D packaging technologies have revolutionized chip interconnection methods and become the key to breaking through the bottleneck of integrated circuit development processes. TSV (Through Silicon Via) technology, as an advanced interconnection method, plays a vital role in 3D IC packaging such as HBM (High Bandwidth Memory) and 2.5D packaging technology such as CoWoS [2], promoting the integrated circuit industry development, the market space is vast .
HBM is an advanced memory technology that stacks DRAM (Dynamic Random Access Memory) chips vertically next to logic chips, greatly increasing memory bandwidth and meeting high-performance requirements.
CoWoS is a 2.5D packaging technology that breaks through the limitations of traditional single packaged chips and achieves high integration and efficient interconnection of different chips through silicon interposers.
The 12-inch deep silicon etching machine PSE V300 launched by Northern Huachuang has gone through iterations and has been recognized by many domestic 12-inch advanced integrated circuit manufacturers. It has become the main machine for TSV mass production lines, and has expanded to power devices, CIS (CMOS Image Sensor, image sensor) and other fields are fully used in major 12-inch mainstream Fab factories in China. Up to now, the installed capacity of the equipment has exceeded 100 cavities, the market share has been increasing year by year, and it is well recognized by customers.
The PSE V300 machine uses a combination of fast gas and radio frequency switching control systems to accurately control the sidewall morphology in deep silicon etching with a high aspect ratio greater than 50:1, achieving no damage to the sidewalls and no damage to the line width. Its process The performance is better than the current industry indicators, with better etching uniformity and selectivity.
In terms of structural system, PSE V300 adopts a single-chip design per cavity, which has better air flow field uniformity and true roundness process performance, ensuring better quality and stability of the semiconductor device manufacturing process. The machine can be configured with 6 chambers at the same time, with excellent productivity and performance. In addition, by optimizing the machine wafer edge protection device, the product yield rate is improved. The effect is better than the current industry product indicators and has been widely praised by the market.
I wasn’t able to find the docket on CourtListener but if “January 2026” is a placeholder, the actual trial date should be much later since in these complex criminal cases, the motions to exclude evidence, the motions for continuance, the motions in liminie, etc, etc will just burn through time
New progress in adaptive microfluidic heat dissipation for microelectronics chips
The team of researcher Jiao Binbin from the Microsystem Technology Laboratory of the New Technology Development Department of the Institute of Microelectronics has made new progress in the field of chip adaptive microfluidic heat dissipation. This study was inspired by the evaporation of sweat from animals through pores to enhance heat dissipation. Based on the bionic principle, a temperature-sensitive valve body structure and a working medium evaporation area were prepared in a silicon-based microfluidic cold plate. When the chip is working under extremely high power consumption conditions and its temperature rises sharply, the temperature-sensitive valve body opens and releases the cooling fluid to the evaporation area to achieve adaptive heat dissipation enhancement of the cold plate. This research provides a feasible heat dissipation method for adaptive microfluidic heat dissipation of high-power density chips.
As Moore's Law slows down, artificial intelligence and high-performance computing (HPC) chips are becoming increasingly popular. Currently, the power consumption level of a single chip has jumped from hundreds of watts to kilowatts. Under the trend of increasing integration and shrinking size, the average chip power density will reach 500W/cm 2 , posing severe challenges to heat dissipation and reliability. Microfluidic heat dissipation introduces cooling fluid into micro-nanoscale channels and quickly transfers chip heat through forced convection heat transfer. It is a new and efficient heat dissipation method. To meet reliability requirements, a constant thermal power threshold is often calculated based on the extreme high power consumption of the chip. However, the operating time under extreme power consumption conditions is less than 10%, which will lead to idleness and waste of cooling resources. Therefore, designing a method to adaptively adjust the heat dissipation power threshold based on the power consumption characteristics of high-power chips is of great significance to improve system energy efficiency.
This study proposes an adaptive dynamic threshold heat dissipation method to replace the traditional constant threshold heat dissipation method. When the chip is working in extremely high power consumption conditions, this method uses bionic sweating behavior to provide additional heat dissipation capability by sacrificing cooling fluid. The silicon-based microfluidic cold plate prepared by this method can achieve a fixed threshold through microchannel forced convection and a dynamic threshold through adaptive evaporation, and use the memory alloy temperature-sensitive valve body structure to control the opening and closing of "pores" and adjust the working fluid. "Evaporate sweat" in the evaporation zone to achieve dynamic regulation of the heat dissipation power threshold. Compared with the traditional microfluidic heat dissipation structure, this cold plate can not only meet the heat dissipation requirements of extremely high power consumption, but also effectively reduce the consumption of heat dissipation resources under normal power consumption, and all the energy required for the adaptive control process comes from the heat generated by the chip itself. , without consuming additional energy. Experiments show that under extreme chip power consumption conditions, adaptive evaporation can increase heat dissipation capacity by 80% and reduce junction temperature by 22.3°C. By further optimizing the hydrophilicity adjustment of the evaporation zone, liquid drainage control and phase change state control, the power density of the chip can be increased by 208W/cm 2 at the rated operating temperature .
As Moore's Law slows down, artificial intelligence and high-performance computing (HPC) chips are becoming increasingly popular. Currently, the power consumption level of a single chip has jumped from hundreds of watts to kilowatts. Under the trend of increasing integration and shrinking size, the average chip power density will reach 500W/cm 2 , posing severe challenges to heat dissipation and reliability. Microfluidic heat dissipation introduces cooling fluid into micro-nanoscale channels and quickly transfers chip heat through forced convection heat transfer. It is a new and efficient heat dissipation method. To meet reliability requirements, a constant thermal power threshold is often calculated based on the extreme high power consumption of the chip. However, the operating time under extreme power consumption conditions is less than 10%, which will lead to idleness and waste of cooling resources. Therefore, designing a method to adaptively adjust the heat dissipation power threshold based on the power consumption characteristics of high-power chips is of great significance to improve system energy efficiency.
This study proposes an adaptive dynamic threshold heat dissipation method to replace the traditional constant threshold heat dissipation method. When the chip is working in extremely high power consumption conditions, this method uses bionic sweating behavior to provide additional heat dissipation capability by sacrificing cooling fluid. The silicon-based microfluidic cold plate prepared by this method can achieve a fixed threshold through microchannel forced convection and a dynamic threshold through adaptive evaporation, and use the memory alloy temperature-sensitive valve body structure to control the opening and closing of "pores" and adjust the working fluid. "Evaporate sweat" in the evaporation zone to achieve dynamic regulation of the heat dissipation power threshold. Compared with the traditional microfluidic heat dissipation structure, this cold plate can not only meet the heat dissipation requirements of extremely high power consumption, but also effectively reduce the consumption of heat dissipation resources under normal power consumption, and all the energy required for the adaptive control process comes from the heat generated by the chip itself. , without consuming additional energy. Experiments show that under extreme chip power consumption conditions, adaptive evaporation can increase heat dissipation capacity by 80% and reduce junction temperature by 22.3°C. By further optimizing the hydrophilicity adjustment of the evaporation zone, liquid drainage control and phase change state control, the power density of the chip can be increased by 208W/cm 2 at the rated operating temperature .
This seems like a big deal to not being reliant on foreign equipment for 2.5D/3D packaging
Sounds like it has already been used in domestic production lines
Has anyone looked into the current TSV capacity currently? I'd be curious to see who is doing it and how much they are able to do
SHANGHAI LINGANG VIGOROUSLY SUPPORTS THE WIDE BANDGAP SEMICONDUCTOR INDUSTRY
Shanghai Global Investment Promotion Conference and the Lingang New Area Wide Bandgap Semiconductor Industry Chain Investment Opportunity Sharing Conference were held. The new area management committee and Lingang Group co-organized the meeting. Nearly two hundred companies and industrial investment institutions in the fields of wide bandgap semiconductors and smart cars attended the meeting. The Lingang New Area Management Committee joined hands with Kaishitong and other companies under Wanye Enterprise (600641.SH) to jointly initiate the establishment of the "Automotive-Wide Bandgap Semiconductor Industry Chain Alliance". Dr. Chen Kelu, general manager of Kaishitong, serves as a key equipment company Representatives attended the founding ceremony of the alliance. Chen Kelu introduced that Keshitong attaches great importance to the development opportunities of wide bandgap semiconductor industries such as silicon carbide. Based on its existing technology accumulation, Keshitong has developed a high-temperature ion implanter for silicon carbide and plans to move it into customer production lines in June this year.
Kaishitong has been committed to independently controllable and domestic substitution of the entire range of ion implantation machines. It adheres to the combination of industry and market demand with technological independence and self-reliance, and has successively realized low-energy large-beam ion implanters, ultra-low-temperature ion implanters and high-energy ion implanters. After the industrialization of the implanter and repeated orders, the first CIS ion implanter, which is extremely technically difficult, was recently delivered, and 8 implanter equipment were shipped in the first quarter. With its excellent ability to continue independent research and development, innovation and industrialization, it has practiced Be the "vanguard" of new quality productivity.
Lens mounting and adjusting equipment and lens mounting and adjusting methods
Beijing U Precision Tech Co Ltd
Abstract
The invention provides a lens assembly and adjustment equipment and a lens assembly and adjustment method, and relates to the technical field of photolithography machines. The lens assembly and adjustment equipment includes an orientation adjustment device, an assembly detection device and an assembly adjustment device. The orientation adjustment device has a bearing position for carrying the lens; the assembly detection device has a position for limiting the lens barrel to a preset assembly position to form an assembly. The limiting position of the lens barrel; the assembly and adjustment device includes a pressure ring, an assembly and adjustment drive assembly, and an adsorption assembly and a clamping assembly connected to the assembly and adjustment drive assembly. This lens assembly and adjustment equipment can efficiently and accurately complete the assembly of the lens and the lens barrel, and the assembly process will cause less damage to the lens.
Xingsi Semiconductor completed over 500 million yuan in Series B financing and is a baseband chip design company.
Xingsi Semiconductor completed a Series B financing of more than 500 million yuan. Investors in this round include China Electronics Data Fund, CDH Hong Kong Fund, Blue Shield Optoelectronics, Huachuang Capital, Langrunlifang, and Xingding Fund , Zhejiang Leikeyao, etc., old shareholder Wofu Venture Capital continues to invest additionally. After the completion of this round of financing, Xingsi will continue to increase its investment in a complete set of solutions in the field of low-orbit satellite communications to ensure and support major strategic satellite Internet projects.
Xingsi Semiconductor focuses on 5G/6G communication technology and can provide integrated air, space and ground chips and solutions for all scenarios, including 5G/6G eMBB, RedCap and NTN’s terminal/mobile phone baseband chip platforms and solutions.
As a platform-based baseband chip design company, Xingsi Semiconductor continues to delve into the research and development and industrial application of advanced technologies such as 5G, 5G-A, 5G NTN, synaesthesia integration, etc. Human-machine self-organizing network, eVTOL synaesthesia, vehicle communication and smart cockpit, 5G FWA fixed wireless access, emergency communication, cluster communication, industrial Internet of Things and industry communication fields.
It is reported that satellite Internet is one of the core businesses of Xingsi Semiconductor . It is actively participating in the research and development work related to the satellite Internet large-scale constellation plan and is a supplier of baseband chips for low-orbit satellite communication terminals. According to official information from Xingsi, it is at the domestic leading level in the research and development of communication baseband chips for the low-orbit broadband satellite evolution system, and is the first to open low-orbit satellite communication calls.
On March 1 this year, Xingsi Semiconductor announced that its first self-developed 5G RedCap CS6601 baseband chip platform successfully passed the China Unicom 5G IoT OPENLAB open laboratory test and obtained the OPENLAB laboratory certification. Nanjing Xingsi Semiconductor is currently the only chip manufacturer that has passed China Unicom’s OPENLAB RedCap chip URLLC L3 level certification.