Chinese semiconductor thread II

tokenanalyst

Lieutenant General
Registered Member

Virtual_N2_PDK: A Predictive Process Design Kit for 2-nm Nanosheet FET Technology.​

Abstract:​

Nanosheet FETs (NSFETs) are considered promising candidates to replace FinFETs as the dominant devices in sub-5-nm processes. To encourage further research into NSFET-based integrated circuits, we present Virtual_N2_PDK, a predictive process design kit (PDK) for 2-nm NSFET technology. All assumptions are based on publicly available sources. Ruthenium (Ru) interconnects are employed for the buried power rail (BPR) and tight-pitch layers. Wrap-around contact (WAC) is also integrated into Virtual_N2_PDK to investigate its impact on circuit performance. By calibrating the BSIM-CMG model with 3-D technology computer-aided design (TCAD) electrothermal simulation results, SPICE models that account for self-heating effects (SHEs) are generated for devices with and without WAC. The simulation results show that with the WAC structure, the energy-delay product (EDP) of standard cells is reduced by an average of 25.18%, while the frequency of a 15-stage ring oscillator circuit increases by 26.05%.​

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tonyget

Senior Member
Registered Member
1.)SMIC achieved a 5-nm-class N+3 node.
2.)SMIC pushed single-exposure DUV resolution from ~38 nm to roughly 35 nm.

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Not really. SMIC N+3 isn't 5nm class yet

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The Kirin 9030 is manufactured using SMIC’s N+3 process, a scaled extension of its previous 7nm (N+2) node. However, in absolute terms, N+3 remains substantially less scaled than industry 5nm processes from TSMC and Samsung. While SMIC has executed notable innovations in DUV-based patterning and DTCO techniques, the process is expected to face significant yield challenges, particularly due to aggressively scaled metal pitch using DUV multi-patterning.
 

tokenanalyst

Lieutenant General
Registered Member
LMAO, sometimes you have to laugh in life. The biggest difficulty that SMIC had before the stringent and out of proportion export controls was not technology but clients. Even their 28nm process was under pressure by TSMC Nanjing and let alone their 14nm. I think if that even if SMIC had access to EUV machines would still have troubles because 1) TSMC would had imported EUV machines in their Nanjing Fab and high profiles client for some reason would had still prefer TSMC.

So the best thing that ever happened to SMIC was to get all the Mainland high profile clients subject to US export controls include the best one: Huawei Hisilicon.
 

antiterror13

Brigadier
It is interesting that White House thinks China can manufacture millions of AI chips in 2026, even more interesting that last June they estimated it was only 200K in 2026 (so something important changed in these few months)

We can confidently assume that White House has access to intelligence info, beyond the think tank "experts" usual public hand-waved data. It is an indirect, but quite strong indication, that localization of 7nm is a done thing, to scale to millions of chips in 2026, it means local technology is ready now, and will be put in mass production shortly.

Is it possible that ASML would totally stop servicing DUVi machine in China ? Would China okay? As my understanding is that all 7nm and below in China are made by ASML DUVi (?)
 

tokenanalyst

Lieutenant General
Registered Member
Is it possible that ASML would totally stop servicing DUVi machine in China ? Would China okay? As my understanding is that all 7nm and below in China are made by ASML DUVi (?)
There is only two ASML DUVi machines that can be used in that node and a both were sold to SMIC before the "October Surprise": the NXT:2000i and the NXT:2050i. According to Mega Stooge Alan Estevez those machines were supposed to be inoperable by now because the lack of mantinience. So you can make your deductions from there.
 

tokenanalyst

Lieutenant General
Registered Member

Oriental Jingyuan has proposed the HPO (Holistic Process Optimization) yield maximization technology route and product design concept.​


The collaborative optimization of design and manufacturing processes (DTCO) is the current mainstream solution to the yield problem in the industry. HPO is based on the development of DTCO, and its core is to maximize the yield in the wafer manufacturing process through comprehensive process optimization. Through HPO, Oriental Jingyuan can help users effectively lower the threshold of chip manufacturing, so that they can also manufacture high-end chips through collaborative optimization under the support of a relatively limited supply chain. This is particularly important for China's semiconductor industry in the post-Moore era.

The implementation of the HPO concept is also of great significance to Dongfang Jingyuan itself. After years of development, based on the HPO concept, Dongfang Jingyuan has achieved deep binding with customers. It not only provides point tools according to customers' existing needs, but also strives to string these tools together to provide customers with a new systematic yield management solution. During the interview, Dongfang Jingyuan made an analogy that the HPO integrated yield solution is somewhat similar to the Hong Kong-Zhuhai-Macao Bridge. The company's computational lithography software products, electron beam equipment, yield management software and other point tools are all bridge piers or relay islands. After nearly 10 years of hard work, now all the "bridge piers" have been erected, and they will be effectively connected in the future to build a "cross-sea bridge".

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Also SMIC is almost sure that is using a lot of domestic DTCO like probably the DJEL Holistic Process Optimization in their effort to get denser features at a decent yield.
 
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