4 Units of SMEE 28nm DUVL will be delivered this year.
Next year it wil be mass produced at a new factory so probably at least a dozen.
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Chinese semiconductor industry
- Thread starter Hendrik_2000
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Next year it wil be mass produced at a new factory so probably at least a dozen.
@WTAN Sir all of it will be delivered to SMIC ? or will be subdivided between Huawei ICRD ,Hua Hong , SMIC and YMTC?4 Units of SMEE 28nm DUVL will be delivered this year.
Next year it wil be mass produced at a new factory so probably at least a dozen.
yes@foofy Sir Xtacking TECH? is XMC part of YMTC?
Just for the purpose of comparing SMEE`s foreseeable production with what has happened recently, does anyone know how many DUV pieces were purchase by SMIC from ASML in the 1.2 billion dollars deal recently announced?@WTAN Sir all of it will be delivered to SMIC ? or will be subdivided between Huawei ICRD ,Hua Hong , SMIC and YMTC?
This whole piece of news regarding XMC/YMTC and Xi'an Ziguang Guoxin is great news. Somebody important, I guess from SMIC, a few posts ago was presented declaring that packing will be just as important as developing EUV equipment.
From a point of view of just the number of transistors in a chip, if you stack four wafers one on top of the other it has the same effect as halfing the nanometers in litography.
I don`t know about speed and power consumption, but considering the developments in XMC/YMTC and the other company, this is definitely the best way of going around Moore`s law.
I thought that piling wafers one on top of the other was just for DRAM memory, but this news seem to say it is going to be used in a greater variety of applications.
Greatest piece of news in quite some time.
And Huawei is working on a new 3d chiplet processor.This whole piece of news regarding XMC/YMTC and Xi'an Ziguang Guoxin is great news. Somebody important, I guess from SMIC, a few posts ago was presented declaring that packing will be just as important as developing EUV equipment.
From a point of view of just the number of transistors in a chip, if you stack four wafers one on top of the other it has the same effect as halfing the nanometers in litography.
I don`t know about speed and power consumption, but considering the developments in XMC/YMTC and the other company, this is definitely the best way of going around Moore`s law.
I thought that piling wafers one on top of the other was just for DRAM memory, but this news seem to say it is going to be used in a greater variety of applications.
Greatest piece of news in quite some time.
@foofy Sir a novice question can YMTC or XMC FAB both DRAM and NAND?
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