Chinese semiconductor industry

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tphuang

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NIO leaving Nvidia for the ET9 and moving to in-house developed Shenji chips.
hmm, not just Nio, but all the Chinese EV makers are doing so. And they all say 1000 TOPS is no problem.

However, NIO, being what it is, decided to go with a 5nm process that currently cannot be handled by SMIC. So if US govt wants to cut them off (for not buying Nvidia chips and for making AI inference chip that's too powerful), they can easily do so.
 

vincent

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hmm, not just Nio, but all the Chinese EV makers are doing so. And they all say 1000 TOPS is no problem.

However, NIO, being what it is, decided to go with a 5nm process that currently cannot be handled by SMIC. So if US govt wants to cut them off (for not buying Nvidia chips and for making AI inference chip that's too powerful), they can easily do so.
Nio bought intelligent suspension system from an American company as well. Don’t think they worry about sanctions at all.
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pecopls

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These are the cores used in the K9000S:
2.62 (TaiShanV120)
2.15 (TaiShanV120)
1.53 (Cortex-A510)

My guess is this K9000SL is a 2.35 GHz TaiShanV120 core with SMT turned on, with another three 2.15 GHz TaishanV120 cores with SMT turned off, and four 1.53 GHz Cortex-A510 cores.
I think you've got the small core and mid-core mixed up.

Take a second look at the screen shot, it lists:
K9000SLK9000S
Large core2 x 2350MHz. Likely SMT.2 x 2620MHz. SMT.
Mid core4 x 2150MHz. Likely SMT.6 x 2150MHz. SMT.
Small core3 x 1530MHz. No SMT.4 x 1530MHz. No SMT.
Total6 SMT cores + 3 non-SMT = 6-core processor, 9 threads.8 SMT cores + 4 non-SMT = 8-core processor, 12 threads.

Based on my understanding, the main difference with K9000S is that(1) the big core frequency is lower, (2) one mid-core was cut, (3) one small-core was cut.
 

gelgoog

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I think you've got the small core and mid-core mixed up.

Take a second look at the screen shot, it lists:
K9000SLK9000S
Large core2 x 2350MHz. Likely SMT.2 x 2620MHz. SMT.
Mid core4 x 2150MHz. Likely SMT.6 x 2150MHz. SMT.
Small core3 x 1530MHz. No SMT.4 x 1530MHz. No SMT.
Total6 SMT cores + 3 non-SMT = 6-core processor, 9 threads.8 SMT cores + 4 non-SMT = 8-core processor, 12 threads.

Based on my understanding, the main difference with K9000S is that(1) the big core frequency is lower, (2) one mid-core was cut, (3) one small-core was cut.
Did you look at the picture in the X/Twitter post? It has four small cores.
 

tphuang

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I think you've got the small core and mid-core mixed up.

Take a second look at the screen shot, it lists:
K9000SLK9000S
Large core2 x 2350MHz. Likely SMT.2 x 2620MHz. SMT.
Mid core4 x 2150MHz. Likely SMT.6 x 2150MHz. SMT.
Small core3 x 1530MHz. No SMT.4 x 1530MHz. No SMT.
Total6 SMT cores + 3 non-SMT = 6-core processor, 9 threads.8 SMT cores + 4 non-SMT = 8-core processor, 12 threads.

Based on my understanding, the main difference with K9000S is that(1) the big core frequency is lower, (2) one mid-core was cut, (3) one small-core was cut.
you are wrong. Please look over the post again. The only differences are what @gelgoog pointed out
 

pecopls

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tokenanalyst

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Jinghe Integrated disclosed the patent of photoresist conveying device to prevent photoresist from crystallizing due to slow flow rate.​


According to the announcement of the State Intellectual Property Office, Hefei Jinghe Integrated Circuit Co., Ltd. has disclosed a patent called "A photoresist conveying device", the authorization announcement number is CN220215547U, and the application date is June 2023. .

1703600960148.png

The patent abstract shows that the utility model provides a photoresist conveying device, which includes a first container, a second container, a first pipeline, a second pipeline and a third pipeline; the first container is used to store photoresist; The first pipeline is used to transport gas into the first container, the output port of the first pipeline is connected to the first container, and the output port of the first pipeline is located close to the top of the first container; the input port of the second pipeline Connected to the first container, the output port of the second pipeline is connected to the second container, and the input port of the second pipeline is located close to the bottom of the first container; the input port of the third pipeline is connected to the glue outlet of the second container Connected to output the photoresist transported into the second container, and the glue outlet is provided at the bottom of the second container. The photoresist transport device uses a pneumatic structure to transport the photoresist to prevent the photoresist from crystallizing due to slow flow rate, and uses the second container as a buffer container to avoid the waste of photoresist during the replacement of the photoresist container.​
 
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