I am starting to think SMIC secretly have more advanced process nodes capacity and with higher yields than some people say they have.
Yuntian Lifei releases large model inference chip: 14nm Chiplet architecture, the first in China!
On November 15, at the 25th China Hi-Tech Fair, Yuntian Lifei launched a new generation of independently controllable edge artificial intelligence (AI) reasoning chips, the DeepEdge10 series, with a maximum computing power of up to 48TOPS and support for D2D/C2C Mash interconnection. Expansion can meet the deployment requirements of large models with hundreds of billions of parameters.
According to reports, Yuntian Lifei DeepEdge10 is China’s first 14nm Chiplet architecture master-level SoC chip for large-model AI reasoning.
Specifically, DeepEdge10 integrates a domestic RISC-V CPU core with 2 large cores + 8 small cores, with a maximum frequency of 1.8GHz; it also integrates a GC8000L GPU with performance comparable to Arm Mali-G52, with a main frequency of 800MHz, and supports a maximum of 8K@ It has 30fps video encoding and decoding capabilities and a maximum JPEG encoding and decoding capability of 200 million pixels, and supports dual-screen differential display (2K@60fps); built-in Yuntian Lifei’s latest generation independent intellectual property NPU NNP400T, with int8 computing power up to 12Tops. At the same time, DeepEdge10 also has hardware-level security features and complete high- and low-speed peripheral interfaces.
View attachment 121437
As mentioned earlier, DeepEdge10 is specifically optimized for large model reasoning needs. Its internally integrated NNP400T NPU is a neural network processor that supports a new computing paradigm for large models. It not only supports FP16/INT16/INT8 and other data format, also supports multi-threading and Transformer network structure model.
View attachment 121438
In terms of manufacturing technology, due to limited access to more advanced manufacturing processes, DeepEdge10 chose to be based on the domestic independently controllable 14nm process. At the same time, it adopts the Chiplet advanced packaging architecture based on D2D (Die to Die) interconnection, which can support flexible expansion of computing power and meet the diverse needs of computing power and cost in different scenarios.
For example, through the advanced packaging technology of D2D Chiplet, by loading more DeepEdge10 Dies into one package, the performance can be doubled. Of course, for advanced packaging technology, it is necessary to ensure that high-speed interconnection, large bandwidth, low power consumption, low latency, high reliability of transmission, powerful routing, and unified memory can be achieved between Die and Die.