I’m well aware of the kinds of reasons that can lead to decisions like relaxing cell densities or other feature sizes, spacing parameters, etc. Yield, manufacturability, and transistor performance all present constraints you need to optimize for at those smaller node scales. Sometimes relaxing some dimensional constraints improves transistor performance so it’s not a complete positive correlation. This is why actually addressing the physics and not just the measurement matters for assessment.Indeed, it's more complicated than just simple shrink to obtain the best Power & Performance. Feature size, capacitance, supply voltage, threshold voltage, Gate width, Gate length, etc. all contribute to Power. But in general, smaller feature sizes has a significant influence on the final performance & power consumption, smaller gate width lead to lower threshold voltage and thus lead to lower leakage and thus lower power cosumption.
more than happy to discuss everything in more detail, for example, on why tsmc actually relaxed M1 CD features relative to CPP going from 7nm to 7nm+. What I provided is a general comparison for general consumption for those not intimatly familiar with ins-and-outs of semiconductor design and fabrication.
Employing “similar process” does not necessarily mean the details around transistor designs and features will be comparable. For example it’s entirely possible SMIC chose to relax certain feature spacings and sizes to preserve better transitor performance and manufacturability based on specifics of their transistor design or manufacturability limits (likely some combination of both).With that said, actual PPA testing of 7nm, 7nm+, 5nm, 3nm do have the same correlation where the smaller nodes with smaller features have better PPACt performance. And since SMIC basically literally have suspiciously similar process to tsmc, you can assume if it has similar feature dimension it will perform relatively similar to the tsmc one.
I am not saying that there isn’t a reason to track those specific feature dimensions. I am just saying those aren’t the only factors that will shape performance. It is worthwhile imo to not discard the actual transistor performance itself when trying to assess transistor performance since transistors are not only their dimensional measurements.Not sure what semiconductor segment you work in, but from a fab process capability standpoint, there is a freakin reason why we track CPP, MMP, cell area, etc.. It's like I said, a general first step of benchmarking that could be done purely on paper. Then subsequent comparison would be to perform actual testing on the actual chip to benchmark PP portion of PPACt. TechInsight does the exact same evaluation, so don't understand what your objection to this methodology is.
I don’t have data per say but I seem to recall that 1) you were very adamant a few years ago arguing that Intel 7, even though it was still “10 nm” should be counted as comparable to TSMC 7 nm based in part on transistor performance, 2) we know some of Samsung’s recent node shrinks (I recall their 5 nm process but also their 3 nm process) have had performance issues despite more aggressive feature shrinking than TSMC.If you have data to show larger CPP, M2 transistor have better PPACt do share that data.. Better yet, since you object to the general benchmarking methodology I shared, why don't you show proof that SMIC N+2 with similar feature size to tsmc 7+nm could outperform tsmc 5nm with smaller features or if PPACt performance of nodes with larger featuers would outperform one with smaller featuers?
I don’t expect N+2 to have comparable performance to TSMC 5 nm, but that is not what I’m arguing here. I’m simply pointing out that reducing everything to feature sizes is not the whole picture. It is a tad more complicated than that and I don’t think that should be obfuscated or hand waved at if you want to be serious about comparative assessment.
If there wasn’t an immersion system we wouldn’t be seeing orders for immersion control equipment.so where is this SSA800 being tested?
why do i have a feeling perhaps 'the street' is confused with testing of SMEE's iline system and confused it to be an immersion system?