Chinese semiconductor industry

tokenanalyst said:

Is way more than the light source.
-There is a need for enhance resolution techniques like immersion liquids
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- Also especial diffractive-refractive optics lens systems.
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-Advance nanopositioning systems
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-Overlay and optics metrology
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-Computational lithography
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-And the photoresist and coating process.

When you add all that to techniques like a multi-patterning process then you can call something that is definitely no 7nm a 7nm process.

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Yes, I know. Just a quick explanation as I was going off.

That is why I added " (Assuming all the other process-node technical challenges are solved) " which of course includes among other things the machine has to be the immersion type for that kind of resolution.

Btw, good graphics there, lol. I'm going to save it on my hard drive.

So if 232 layers were to build in one deck, the etch channel aspect ratio would have been 109:1. YMTC 232 layers uses two deck，128 layers form Deck 1 and 125 form deck 2. Does that mean AMEC's 64:1 etching device is good enough for YMTC 's 232 layers NAND production？

At the very heart of the manufacture of all YMTC’s 3D NAND chips is the Xtacking approach. Known as YMTC’s hallmark, Xtacking involves the use of two separate wafers, whereas only one wafer is traditionally employed. It consists of building the NAND dies by joining a CMOS wafer and a NAND array wafer face to face, the two wafers being bonded together using metal pads. Both wafers can be manufactured simultaneously, enabling the manufacturer to shorten the production cycle in case of high memory demand.

A cross-sectional view of the die shows that two decks of alternating tungsten wordlines and SiO layers are formed one after the other. This method was adopted to reduce high aspect ratio etching. If built in one deck, the etch channel aspect ratio would have been 109:1, which would have resulted in very complex trench etching and filling processes and a higher etch defect number.

The strategy is always to find the right balance between yield losses and the cost induced by repeating the etching process. Two hundred fifty-three wordlines are observed in the vertical NAND string; 128 layers form Deck 1 and 125 form deck 2. Besides the 232 active layers, the remaining ones are divided between dummy and selection layers.

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百合光学发力纳米级光刻机光源突破

Baihe Optics makes a breakthrough in the light source of nanoscale lithography machine


在专业技术要求更高的纳米级光刻机领域，百合光学已向中芯国际供应20多种光学元器件，其中10余种已通过中芯国际验证，成为中芯国际光学元器件战略供应商。

上海微电子是国内光刻机研发的希望，其光刻机反光碗由百合光学独家供应。“在国内，反光碗能达到上海微电子要求的只有百合光学一家，我们是唯一供应商。”孙昊称。

据了解，百合光学生产的反光碗具有光强好，精度高，光谱达标，均匀性达标等技术优势，光学性能媲美国外进口产品。

In the field of nano-level lithography machines with higher professional technical requirements, Baihe Optics has supplied more than 20 kinds of optical components to SMIC, more than 10 of which have passed SMIC's verification and become a strategic supplier of SMIC's optical components.

Shanghai Microelectronics is the hope for the research and development of domestic lithography machines, and its reflective bowls for lithography machines are exclusively supplied by Baihe Optics. "In China, Baihe Optics is the only company that can meet the requirements of Shanghai Microelectronics for reflective bowls, and we are the only supplier." Sun Hao said.

It is understood that the reflective bowl produced by Baihe Optics has technical advantages such as good light intensity, high precision, up-to-standard spectrum, and up-to-standard uniformity. The optical performance is comparable to imported products from the United States.

tonyget said:

So if 232 layers were to build in one deck, the etch channel aspect ratio would have been 109:1. YMTC 232 layers uses two deck，128 layers form Deck 1 and 125 form deck 2. Does that mean AMEC's 64:1 etching device is good enough for YMTC 's 232 layers NAND production？

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Hybrid bonding?

Well, in the past few days, some people are posting this. Not sure where it came from.

But according to the earlier poster, HW has a stack of Snapdragon around which will be paired with 5G chipset to give upcoming HW phones 5G capabilities. And then they anticipate getting cut off from QCOM chips and that's when the Kirin chips will need to come back from low to medium ranged phones. They do need a huge stack of snapdragon though. Apparently, heat related issues with 14nm process produced 5G chip have been resolved. Remember, the original Balong was on 7nm process, so getting 14nm to achieve same performance is higher. As I discussed previously, they need all the 7nm production they can get for SoCs.

If SSA800 is good enough for 7nm process, then in a couple of years, they will have all domestic 7nm and SMSC can expand to as much 7nm capacity as they can afford. But until then, 7nm is quite limited, So snapdragon SoCs need to last another year.

on the topic of 5G, it seems like Sai Micro's BAW filter partner is actually 武汉敏声 (Memsonics )

This was the article on their production line with Sai Micro in Beijing opening back in Dec 2022

more recently Memsonics said

武汉敏声北京分公司总经理李春江详细介绍了产线进展情况，并展示了产线试生产的BAW滤波器产品，他提到：“敏声-赛莱克斯北京8英寸BAW滤波器联合产线是国内屈指可数的BAW滤波器大规模量产线之一。产线的通线，标志着武汉敏声正式踏入具备滤波器设计、制造、销售全流程实力的CIDM/IDM厂商行列，可进一步发挥敏声核心专家团队平均十年以上的工艺制程经验优势，通过对核心工艺的自主掌控，未来敏声有望在产品性能、产品迭代速度、产品成本控制等方面占据竞争优势，真正解决国产高端滤波器卡脖子问题。”

正如大家看到的最新测试结果，敏声BAW滤波器的产品性能已达到国际先进水平，在插损、滚降、远端抑制等具体性能指标上优于目前国外同类产品，随着产线通线，预计明年将实现多款产品的大规模量产。敏声的滤波器产品，无论在IP设计还是工艺路线上均有独立自主的知识产权，公司已经申请了200余项发明专利，授权了近70项发明专利。下一步，我们将继续秉承初心，保持匠心，不断优化迭代现有产品，同时专注研发更高频段、更大带宽的高性能BAW滤波器，保持

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优势，持续为客户提供性能优良、安全、稳定的产品组合。”

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They are fully ready for high end BAW filter mass production and cost is down. 5G is no longer an issue. Qorvo stocks are in trouble imo

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7月3日接待机构调研时表示，公司与武汉敏声以共同购置设备的方式合作建设的北京8英寸BAW滤波器联合产线已于2022年底实现通线，双方一直就数款BAW滤波器开展相关工作，工艺开发及试产工作符合预期，专线产品类别增加，良率水平大幅提升，量产事宜正在积极准备中。该产线初期建成的产能为2000片晶圆/月，后可扩展至1万片晶圆/月的水平。

7月7日，武汉敏声新技术有限公司与北京

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股份有限公司合作共建8英寸FBAR滤波器产线项目首台核心工艺设备搬入仪式，在北京经开区赛微电子Fab3厂房外隆重举行。武汉敏声董事长孙成亮、赛微电子董事长杨云春以及多位产线建设技术人员共同参加本次仪式。
自2021年8月武汉敏声与赛微电子达成战略合作，开启共建8英寸FBAR滤波器产线项目，双方在11个月时间内紧锣密鼓、通力合作，在今天迎来里程碑时刻。自此，敏声滤波器产线建设将进入设备搬入安装阶段，按规划进展将在今年年底完成项目通线

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so 10k wpm eventually. Maybe that's enough for 10 million chips per month? BAW filter, should be pretty small. I would imagine. 1000 per 8-inch wafer is my guess, but who knows. They've been working together on this since August 2021. So, it's taken a while to break the barrier

Another thing to think about
Huawei said about it

前，射频芯片这个领域基本上是被欧美和日本的5家巨头所牢牢把控。分别为村田电子 (Murata)思佳讯 (Skyworks)、博通 (Broadcom) 、威讯联合半导体(Qorvo)、高通 (Qualcomm)。

此前华为独立荣耀就是为了能确保其接上高通的射频芯片及滤波器，华为余承东曾表示“只要有BAW,就能实现5G”

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tonyget said:

So if 232 layers were to build in one deck, the etch channel aspect ratio would have been 109:1. YMTC 232 layers uses two deck，128 layers form Deck 1 and 125 form deck 2. Does that mean AMEC's 64:1 etching device is good enough for YMTC 's 232 layers NAND production？

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It seems they have made each layer thinner too:

As the number of layers has doubled, it was expected that the die thickness would be doubled too. What was true from generation 2 to generation 3 (4.4 µm versus 8.6 µm) is not the rule for generation 4 (11.9 µm). To minimize the total height of the stack, YMTC has reduced the wordline pitch by 20% compared to the previous generation.

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I'm not an expert but it seems that if the total height is reduced it means that with the same 64:1 max aspect ratio you can etch more layers, because in the given max height of the device, given by the 64:1 aspect ratio, you can pack more layers....

So answering to your question: "Does that mean AMEC's 64:1 etching device is good enough for YMTC 's 232 layers NAND production?" I would say, it depends on the single layer's height...and they made it 20% thinner maybe just for this reason.

european_guy said:

It seems they have made each layer thinner too:



I'm not an expert but it seems that if the total height is reduced it means that with the same 64:1 max aspect ratio you can etch more layers, because in the given max height of the device, given by the 64:1 aspect ratio, you can pack more layers....

So answering to your question: "Does that mean AMEC's 64:1 etching device is good enough for YMTC 's 232 layers NAND production?" I would say, it depends on the single layer's height...and they made it 20% thinner maybe just for this reason.

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Being able to make the layers thinner is a proof of capability, not a workaround for lesser capability.

Their 96 layer etching machine is in the verification process. So is probably that is already being use in trial production.

european_guy said:

It seems they have made each layer thinner too:



I'm not an expert but it seems that if the total height is reduced it means that with the same 64:1 max aspect ratio you can etch more layers, because in the given max height of the device, given by the 64:1 aspect ratio, you can pack more layers....

So answering to your question: "Does that mean AMEC's 64:1 etching device is good enough for YMTC 's 232 layers NAND production?" I would say, it depends on the single layer's height...and they made it 20% thinner maybe just for this reason.

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　　Zhongwei Company has further improved its layout in the field of thin film deposition equipment by participating in Tuojing Technology. The 28-nanometer chip production line has also undergone 14-nanometer process verification, and the 3D memory chip production line supports the production of 64-layer 3D NAND chips, and is verifying the measurement performance of 96-layer 3D NAND chips. In the short term, the "de-J" trend and the "Micron review" event-driven companies have become the focus, and the importance of Micron in the high-barrier big track has become prominent. In the medium and long term, after reviewing the two leading companies AMAT and LAM Growth history, AMAT started with thin film deposition technology and then expanded to etching and other technologies to build platform barriers; LAM started with etching technology and then entered into thin film deposition and other fields to open up the growth ceiling, all of which succeeded in the core high barrier competition in the early stage of development At the same time, the two leading companies have a rich history of extension mergers and acquisitions, which is similar to the strategic planning/development trend of China Micro.

latenlazy said:

Being able to make the layers thinner is a proof of capability, not a workaround for lesser capability.

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?

I didn't mean to minimize the achievement, I just noted that if your etch supplier (AMEC in this case) gives you a 64:1 aspect ratio machine and you want to increase the layers, you may need to thinner them. As simple as that, no other intentions on my part.

european_guy said:

?

I didn't mean to minimize the achievement, I just noted that if your etch supplier (AMEC in this case) gives you a 64:1 aspect ratio machine and you want to increase the layers, you may need to thinner them. As simple as that, no other intentions on my part.

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Ah sorry, misunderstood. I thought you were saying AMEC was the reason they had thinner layers. Was a bit confused by your comment at first but that’s clearer now.