Chinese semiconductor industry

Dongxiang County and Hangzhou Xinlei Semiconductor Technology Co., Ltd. successfully signed a large-scale integrated circuit diamond substrate production base project​

On May 14, at the Investment Promotion Conference for Key Industries of Gansu Province held in Hangzhou, Zhejiang Province, Ma Liangzuo, deputy secretary of the county party committee and county magistrate, and Fan Yongbiao, CEO of Hangzhou Xinlei Semiconductor Technology Co., Ltd. signed a large-scale integrated circuit diamond substrate production base project investment agreement.

The total planned investment of the project is 1.5 billion yuan, and it is planned to purchase 200 sets of R&D, inspection, analysis, and testing equipment for fourth-generation semiconductor production equipment, and gradually build a fourth-generation semiconductor production base in Dongxiang County. At present, the project laboratory is under construction simultaneously, and two experimental equipments have been transported to Dongxiang Economic Development Zone.

a lot of people are getting excited by this news

keep in mind that this has been rumored for a while now and whatever comes out may not actually be called A2 or be that advanced. Huawei is likely going to need a separate 5G chip (new Balong) to get phones to work in 5G.

they will get competitive GPGPU and server CPU before they can be competitive in the smartphone SoC market

tphuang said:

a lot of people are getting excited by this news

Please, Log in or Register to view URLs content!

Please, Log in or Register to view URLs content!

keep in mind that this has been rumored for a while now and whatever comes out may not actually be called A2 or be that advanced. Huawei is likely going to need a separate 5G chip (new Balong) to get phones to work in 5G.

they will get competitive GPGPU and server CPU before they can be competitive in the smartphone SoC market

Click to expand...

not an expert in chip architecture but it seems to me that 28 nm is sufficient for machine learning and servers, and that the first deep learing ASICs were Chinese, fabricated on 65 nm???

In this study, we present an ML accelerator called PuDianNao, which accommodates seven representative ML techniques, including k-means, k-nearest neighbors, naive bayes, support vector machine, linear regression, classification tree, and deep neural network. Benefited from our thorough analysis on computational primitives and locality properties of different ML techniques, PuDianNao can perform up to 1056 GOP/s (e.g., additions and multiplications) in an area of 3.51 mm^2, and consumes 596 mW only. Compared with the NVIDIA K20M GPU (28nm process), PuDianNao (65nm process) is 1.20x faster, and can reduce the energy by 128.41x.

Click to expand...

Google has its own versions implemented on 28 nm in 2017 (when 7 nm was leading edge).


This is telling me that even for compute intensive applications, 28 nm is actually pretty good for non-mobile applications, and any FinFET is really, really good.

FairAndUnbiased said:

not an expert in chip architecture but it seems to me that 28 nm is sufficient for machine learning and servers, and that the first deep learing ASICs were Chinese, fabricated on 65 nm???

Please, Log in or Register to view URLs content!

2014	DianNao Please, Log in or Register to view URLs content!	ICT, CAS	digital	vector Please, Log in or Register to view URLs content!	scratchpad	Please, Log in or Register to view URLs content!	452 Gops (16-bit)
DaDianNao Please, Log in or Register to view URLs content!	ICT, CAS	digital	vector MACs	scratchpad	VLIW	5.58 Tops (16-bit)
2015	ShiDianNao Please, Log in or Register to view URLs content!	ICT, CAS	digital	scalar MACs	scratchpad	VLIW	194 Gops (16-bit)
PuDianNao Please, Log in or Register to view URLs content!	ICT, CAS	digital	vector MACs	scratchpad	VLIW	1,056 Gops (16-bit)

Please, Log in or Register to view URLs content!

Google has its own versions implemented on 28 nm in 2017 (when 7 nm was leading edge).

Please, Log in or Register to view URLs content!

This is telling me that even for compute intensive applications, 28 nm is actually pretty good for non-mobile applications, and any FinFET is really, really good.

Click to expand...

All will depend of the on the chip architecture, if power is not an issue then is possible to get more computing power by using specific dedicated made circuitry or advance packaging techniques or a combination. The problem is that new architectures require new ecosystems, that is what made Nvidia really popular, their ecosystem is really good.

SMIC's "semiconductor structure and its formation method" has been granted patent authorization

Changxin memory semiconductor structure detection method related patent announcement

A little more snippet of what I caught on the earnings call

答环节中，就“第一季度公司出货量下降，平均销售单价提升，12英寸和28、40纳米方面，哪些应用比较强劲？8英寸方面，哪些应用比较薄弱？二季度是否看到8英寸情况改善，12英寸仍然有良好的势头吗？”，公司回复称，第一季度，下降的主要是8英寸产品，所以在较低的产能利用率和收入的情况下，平均销售单价有所提升。一季度失去的晶圆订单主要来自低端标准产品。这类产品价格较低，主要在8英寸生产，如低端摄像头，指纹芯片，大屏显示驱动芯片等。二季度，公司收入和产能利用率预计有所恢复，急单主要是来自12英寸特别是40纳米和28纳米的新产品。40纳米和28纳米已恢复到满载，复苏的领域包括DDIC，摄像头、LED驱动芯片等。这种复苏主要发生在中国，背后的原因是，我们看到供应链正在洗牌。新的供应商进入了供应链，他们拿到了订单和市场份额，幸运的是，这些新加入者是公司的客户。所以我们看到的公司的复苏，不一定是整体市场的复苏，而是公司市场份额提升了。

Click to expand...

Again, SMIC not chasing price sensitive market. They are working up the food chain with new DDIC, LED, camera (CMOS?) chips. And it seems like SMIC is finally getting more ability and qualifying for these products

问答环节中，就“公司客户的库存水平看起来很高，客户会保持高库存或缩减库存到更低水平吗？”，公司回复称，对于旧产品或标准产品，市场的库存仍然很高。因此，客户的主要工作仍然是保持一定的库存水位甚至是去库存，公司需要做的是根据长协，来预估出客户需要几个月来消耗掉库存。同时，公司收到了一些急单，主要来自于新产品，而新产品在市场上几乎没有库存。公司面临的挑战是，有很多的新产品进来，需要时间来制作光罩，以及与客户一起完成验证。因此，新产品快速上量是公司在今年下半年和明年复苏的关键

Click to expand...

These new client and orders will lead to recovery in second half of this year and next in the 40 to 28 nm segment

答环节中，就“今年在工艺平台或制程结构上会有新的变化吗？”，公司回复称，第一、今年看到客户需要的都是有一些新性能的产品，即便是在原来的成熟节点，都有一些新的要求。公司今年的重点就是把原来的已有产品迭代，比如像嵌入式存储、高压、特殊存储类的产品从40纳米迭代至28纳米，BCD产品从90纳米迭代至65纳米，提升原有产品的竞争力。如果保持在原有节点做，耐压要变得更高，功耗要变得更小，所以，原来公司最大宗的这些产品都要有新的平台推出。第二、我们原来在消费电子和工业里面的产品都要做成可以兼容汽车级，能通过车规验证。第三、增加产品类型，特别是汽车功率电子的产品做得更多一些，争取能够布全，能够支持大客户的要求

Click to expand...

market is changing, high voltage, embedded memory, special memory project are moving from 40 to 28nm, BCD product going from 90 to 64nm. SMIC has to improve quality of its products to keep up. It also needs to have auto grade qualified power electronics to win general orders.

Very important what's happening. Since they are adding 340k wpm of 28 to 180nm (probably mostly 28 to 90nm) over the next 5 years, they need to win a lot of market share and customers from TSMC and UMC and Samsung

FairAndUnbiased said:

not an expert in chip architecture but it seems to me that 28 nm is sufficient for machine learning and servers, and that the first deep learing ASICs were Chinese, fabricated on 65 nm???

Please, Log in or Register to view URLs content!

2014	DianNao Please, Log in or Register to view URLs content!	ICT, CAS	digital	vector Please, Log in or Register to view URLs content!	scratchpad	Please, Log in or Register to view URLs content!	452 Gops (16-bit)
DaDianNao Please, Log in or Register to view URLs content!	ICT, CAS	digital	vector MACs	scratchpad	VLIW	5.58 Tops (16-bit)
2015	ShiDianNao Please, Log in or Register to view URLs content!	ICT, CAS	digital	scalar MACs	scratchpad	VLIW	194 Gops (16-bit)
PuDianNao Please, Log in or Register to view URLs content!	ICT, CAS	digital	vector MACs	scratchpad	VLIW	1,056 Gops (16-bit)

Please, Log in or Register to view URLs content!

Google has its own versions implemented on 28 nm in 2017 (when 7 nm was leading edge).

Please, Log in or Register to view URLs content!

This is telling me that even for compute intensive applications, 28 nm is actually pretty good for non-mobile applications, and any FinFET is really, really good.

Click to expand...

Do you mean by the ASIC or GPUs or something else? I would think for most GPGPUs, you need at least 7nm to be competitive. I guess with advanced hybrid bonding we've seen, maybe not? In terms of power consumption, cooling and things like that, anything that's not Finfet would seem to be problematic.

tphuang said:

Do you mean by the ASIC or GPUs or something else? I would think for most GPGPUs, you need at least 7nm to be competitive. I guess with advanced hybrid bonding we've seen, maybe not? In terms of power consumption, cooling and things like that, anything that's not Finfet would seem to be problematic.

Click to expand...

Based on my reading, DLP chips are like GPGPUs taken to an extreme. GPGPUs are used for handling massively parallel 32 bit or (now) 64 bit data operations. This is expected as GPUs for actual graphics have to handle 24-30 bit color for existing monitors.

But if you cut the precision required to 16 bit or even 8 bit, requirements drop like a rock to the point where 65 nm DLP is faster than 28 nm GPU (as shown in the prior Chinese paper).

An example of 8 bit data is language where 1 byte is sufficient to describe all Latin letters/numbers. Google TPU is 8 bit only. You can handle all Chinese characters in 16 bit format (2 byte). Chinese DianNao DLP are all 16 bit. So at least for language AIs, you don't need 32 bit data. And if you drop image recognition to grayscale, 8 bit grayscale is really good already. 16 bit color isn't that bad either.

PS: based on the DLP wiki page, this sort of architecture was invented by Chinese institutions.