antiterror13
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Wondering whether all Chinese military chips produce by CETC ?
Chinese semiconductor industry
- Thread starter Hendrik_2000
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Wondering whether all Chinese military chips produce by CETC ?
The Nexchip numbers are in RMB and it’s ASP for 12” whereas HH’s is 8” equivalent ASP.
Nexchip’s 8” equivalent ASP of $600 is just a tad higher than HH’s $581. HH’s wafer mix, having more older nodes drags down its overall ASP number.
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While researching into this, I found this
it makes sense to me that SRAM used for caching would have harder time to shrink than your regular logic transistor section, because DRAM also has the same issue with lowest density at 10nm from what I hear.
And there is no way you can build CPU or GPUs without a large cache. As processing needs increase, so does need for accessing larger caching, since it's much faster than DRAM. One of the keys to developing high performing CPU is having a well designed levels of caching.
So if you can't shrink caching at all after 5nm & can barely shrink after 7nm, then at some point, I think you will reach the point of diminishing returns in ever higher cost of packing more logic transistor.
IIRC, @FairAndUnbiased mentioned that as you get to more advanced nodes with higher densities, there is also higher % of dark transistors that can't be accessed. Any link on that, btw?
I could be entirely wrong here, but it seems like once you get to something between 5 and 7nm process, shrinking further & packing more transistors won't get the scale of improvements compared to 28nm to 14nm
So improvements to CPU/GPU performance probably reside in more improved designs like what we see with this Houmo chip and more improved 3D packaging to get memory & logic die closer to each other and to improve the bond between them
btw, new patent from Huawei on advanced packaging. I actually don't understand this at all, so I will let you guys figure it out
From Huawei whisper
I think what he says here is entirely expected.
Being restricted to 7nm for a couple of years is not ideal, but with improved packaging and software. At least for AI, HPC and EVs, Huawei imo should be competitive here
This is the description of the patent for more context:
technical field
The present disclosure relates to the field of semiconductor manufacturing for producing low cost and high performance small semiconductor devices. In particular, the present disclosure relates to semiconductor packages and a method for producing such packages, such as molded-in modules and sub-modules.
Background technique
Semiconductor manufacturing continues to improve in order to produce smaller semiconductor devices. Smaller devices typically consume less power, have higher performance, and can be produced more efficiently. Additionally, smaller semiconductor devices have a smaller footprint, which is desirable for smaller end products. Smaller semiconductor die sizes can be achieved by improving front-end processes, resulting in semiconductor dies with smaller, higher density active and passive components. Back-end processes can produce semiconductor device packages with smaller footprints by improving electrical interconnect and packaging materials. In addition to laminate embedding, mold embedding is known as a concept to achieve such optimized or derivative packaging, such as pre-packages or subassemblies. One advantage of mold embedding is the high flexibility with respect to the structure to be embedded. The topography of the substrate, chip and contact elements can be easily embedded in the mold compound, whereas laminate embedding requires cutting these features out of the prepreg material.
However, one disadvantage of current mold embedding is its high production cost, whether it is the galvanic deposition of the studs or the laser drilling of the through-holes required for the reference marks.
Contents of the invention
The present disclosure provides an efficient semiconductor manufacturing solution using die embedding without the disadvantages described above. In particular, an alternative mold embedding solution is provided which achieves cost reduction and provides efficient and reliable manufacturing of semiconductor packages.
The foregoing and other objects are achieved by the features of the embodiments. Further implementation forms are evident from other embodiments, the description and the figures.
The basic idea of the present disclosure is to use coated Cu (copper) balls for through-die interconnection purposes. For example, these coated Cu spheres can be applied by re-melting the Sn(Tin) coating using laser energy for single sphere placement or by pressureless sintering. The Cu spheres can be partially ground during the fabrication process to achieve the advantages of good thermal and electrical conductivity, and can be directly soldered or sintered on the open Cu surface. Another advantage of partially ground Cu spheres is the ability to provide perfect interconnects to any RDL (Redistribution Layer) deposited on top of the die.
In other words, this disclosure introduces a novel mold embedding technique that uses vertical interconnect elements composed of coated Cu balls; connects the Cu balls to the substrate by welding, diffusion bonding, or sintering; embeds the Cu balls in the mold layer; and connecting the Cu balls to the redistribution layer by partially cutting the Cu balls, for example, milling the mold layer, and depositing the redistribution layer on top of the mold compound.
Accordingly, the present disclosure proposes a novel vertical interconnection technique using, for example, Sn-coated Cu balls as interconnection elements. This novel interconnection technique results in high temperature stability due to the method of diffusing the solder, i.e., no Ni plating or sintering of the balls. Due to the available and proven equipment for ball placement, good manufacturability can be achieved, for example, a high throughput of about 5 balls per second or more can be achieved. Due to the panel production concept (eg 500x600mm), good manufacturability can be achieved. Novel interconnection techniques allow for excellent height compensation (e.g., ±35 μm tolerance for SiC chips), since the contact area is wider after the milling step, eliminating the need for precise focal depths or plating heights, which are ball geometries The advantages. Due to the wider contact area available after the milling step, a low-cost next interconnection step for soldering or sintering leads can be performed.
Could I ask what you meant by “started out with substantial investment from Powerchip”? Powerchip still has big share of Nexchip after the IPO, no?
Powerchip is known as a “Nikon” fab with Nikon as the tool of record for dry scanners. No surprise Nexchip took after Powerchip’s tool of record.
No they don’t. Nexchip doesn’t have its own maskshop and neither does Powerchip. What you underlined doesn’t equal to Nexchip “make its own mask”
I think it said “mask design”, but what it really means is mask design layout preparation (layout alignment marks, test patterns required by the fab and merchant mask shops, apply OPC to the design, etc.)
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