Core Technology Releases CAPiC Die and Advanced Packaging Technology Platform
The innovative achievements of CAPiC die and advanced packaging technology platform mainly include six core packaging technologies, high-density rewiring fan-out structure ( FOCT-R ), high-density through-silicon via fan-out structure ( FOCT-S ), rewiring and silicon Embedded substrate fan-out structure ( SETiS/RETiS ), stacked chip fan-out structure ( TMV-POP ), glass-based fan-out structure ( TGV-POP ), resin / dry film fan-out structure ( eWLB-F/eWLB- M ). This release embodies the strong technical strength and innovation ability of the Advanced Packaging Technology Research Institute of Sintech.
In recent years, the Sintech Research Institute team has focused on the development of Chiplet -related technologies, striving to provide customers with more and better advanced packaging technology solutions, especially through high-density wafer-level RDL integration to reduce the number of substrate design layers , and even achieve the role of replacing the substrate.
Zhang Zhong, vice president of technology of Xinde Technology, gave a detailed introduction to the six major packaging technologies of CAPiC die and advanced packaging technology platform:
1 ) FOCT-R ( FANOUT Connected Tech-RDL ) , mainly used in data centers , server CPUs , computing AI, IOT chips, realizes the interconnection between homogeneous and heterogeneous chips, and can integrate two substrates with different characteristics : A substrate with a high number of layers, a more precise rewiring interposer ( RDL Interposer ), can further realize a larger 2.5D package, and reduce the number of substrate layers. Using redistribution and bump technology, the minimum line width of 2 μm and the wiring of 2um spacing are realized. At the same time, Sintech launched single-chip HPFO technology, using Interposer to effectively reduce the number of substrate manufacturing layers.
2 ) FOCT-S (Fanout Connected Tech- S), dedicated to high-performance computing ( HPC ), artificial intelligence ( AI ), data centers and network products that require high-performance and large-area packaging technology, using silicon transfer boards ( Si Interposer ), which can achieve higher precision ( <1um line width and spacing) rewiring layer, achieve higher density connections, provide higher performance, and give full play to the advantages and characteristics of 2.5D packaging eWLB-M, the main application For the fan-out packaging of medium and large chips , the package size can be around 8x8~15x15mm . Using rewiring and bump technology, the chip can be directly connected to the chip, reducing the thickness, reducing the connection loss, reducing the cost, and cost-effective. Applied to millimeter wave, radio frequency and wireless chip packaging, processor and baseband chip packaging;
3 ) SETiS/RETiS ( Silicon Embeded Tech in Substrate/ RDL Embeded Tech in Substrate ) , an embedded multi-chip interconnect bridge, can realize the interconnection of heterogeneous and homogeneous chips, and the cost is lower. The realization includes CPU , graphics card, memory , IO and other communication among multiple chips, by embedding the rewiring layer interposer ( RDL Interposer ) into the substrate, the communication efficiency between chips can be improved, the loss can be reduced, and the substrate can be reduced without increasing the thickness of the package. Design difficulty and number of layers.
4 ) TMV-POP is mainly used in high computing power packaging. After interconnecting homogeneous or heterogeneous chips through the rewiring adapter board, the interconnection part is introduced into the back of the package through high copper pillars and plastic encapsulants. Lead out the bumps and interconnect with another package again, realize the interconnection between the package and the package without increasing the package plane size, provide performance, and give full play to the advantages of different packages.
5 ) TGV-POP, mainly used in radio frequency chip packaging, has the advantages of high density, low warpage ( CTE match ), high reliability, low loss factor, low chip offset, low warpage, etc. The package uses glass The insulator material greatly reduces the substrate loss and parasitic effect, ensures the integrity of the transmission signal, rewiring on the glass, transfers the bumps and on this basis, the package interconnection between the chip and the chip fully meets the high frequency signal transmission requirements;
6 ) eWLB-F& eWLB-M, mainly used in the fan-out packaging of small chips , the package size can be around 0.6x0.6~15X15mm , using refined ABF film and wafer-level molding solutions, and then wiring And bump technology, the chip is packaged and protected most efficiently, and multiple chips can also be interconnected to achieve the smallest package size, reduce costs, and cost-effective. It can be used for analog chips, audio playback, voltage protection and other chips. This solution can Effectively replace part of the substrate manufacturing requirements and realize the transformation from FCCSP to FANOUT-CSP .