Chinese semiconductor industry

PopularScience said:

They are selling second hand NXT2050i in China. How are them going to ban export to China?

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Thru a middleman? sorry bro I can't fathom, NXT 2050i was introduced in late 2020, so maybe somebody earn a lot of commission reselling new NXT 2050i as second hand to escape sanction? If true then ASML is complicit cause the buyer will surely want the maintenance and after service of the product unless ASML China will warrant that service.

If China can do it, then it is simple.
If China cannot do it, then it is complex

@tonyget

ansy1968 said:

Thru a middleman? sorry bro I can't fathom, NXT 2050i was introduced in late 2020, so maybe somebody earn a lot of commission reselling new NXT 2050i as second hand to escape sanction? If true then ASML is complicit cause the buyer will surely want the maintenance and after service of the product unless ASML China will warrant that service.

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This company can provide maintenance. Looks like a serious company.

tonyget said:

Even with all of above，it still took ASML more than a decade to commercialize EUV. So what makes you think that China can get it done in 4/5 years？

There are those who think China can never make EUV，there are also those who think China can make EUV in no time. I fall in the middle，I think China can make EUV，in a decade.

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It's possible for China to make EUV in half the time it required ASML to achieve it.

The main reason is: China would be using latest math and technical tools, incl AI etc. to achieve their goal.

Some examples are: after US & USSR detonated atomic devices, 10+ years later China was starting their project, with latest tech/chemistry publication and technical papers, and perhaps other better tools.

Or, the rover mission to Mars where CN did it single-shot in record time.

Other factors could accelerate dev:
1. increase funding 2-3x
2. Hire more scientists
3. Work 24hrs a day (which ASML might not have done so)

hvpc said:

it is what it is. 3D NAND from an dimensional sizing and architectural complexity standpoint is indeed much simpler than DRAM and LOGIC. PERIOD.

if you are going to twist actual technical facts into what you said, you really have an inferiority complex issue going on.

don’t knock technical facts if you don’t know much about it.

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the post is about technical detail

This article is only for reference.

tonyget said:

DRAM is much more complex than NAND，it's alot more than just what tools available，not surprising that CXMT lags behind.



Yes，YMTC's future expansion all depends on how soon domestic equipments will be up to the task

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3D NAND 232 layers is highly complex, especially 3D Xtacking 3.0 technology, very advanced technology

antiterror13 said:

3D NAND 232 layers is highly complex

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yes. Required 40 types of etching machines.

hvpc said:

it is what it is. 3D NAND from an dimensional sizing and architectural complexity standpoint is indeed much simpler than DRAM and LOGIC. PERIOD.

if you are going to twist actual technical facts into what you said, you really have an inferiority complex issue going on.

don’t knock technical facts if you don’t know much about it.

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CD isn't the only measure of complexity or challenge. 3D NAND has to deal with issues like wafer bow and interface strain from having 100+ layers of thin film structures on it, plus extremely high aspect ratio etching. The overlay of 100+ thin films is also not trivial.

PopularScience said:

the post is about technical detail

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nothing in that post is technical, just bunch of qualitative mumble jumbo.

I was referring more to your comment:

FairAndUnbiased said:

CD isn't the only measure of complexity or challenge. 3D NAND has to deal with issues like wafer bow and interface strain from having 100+ layers of thin film structures on it, plus extremely high aspect ratio etching. The overlay of 100+ thin films is also not trivial.

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what you listed is much easier to tackle.

increasing difficulty of shrinking nodes over the year is due to the shrinking error tolerances. don’t tell me you are not aware 3D NAND has much larger feature sizes and larger error tolerances?

there is a reason why people are making 3D NAND still mostly with old reused tools from older DRAM nodes.