Also LPDDR5，which is main stream on today's smartphone
Chinese semiconductor industry
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Also LPDDR5，which is main stream on today's smartphone
Maybe you are referring to this company
The domestic high-performance computing "three-piece" IP solution is released to meet the bandwidth requirements of the new generation of SoC
In the digital age, data storage, computing, transmission, and application requirements have become new driving forces. High-end chips such as cloud services and high-performance computing are inseparable from the support of underlying IP, especially DDR technology, Chiplet, and high-speed SerDes. Heavy. For high-computing SoC scenarios such as CPU/GPU/DPU/NPU commonly used in HPC, Innosilicon has launched a common IP platform centered on the " three-piece set " of high-performance computing.
The " three-piece set " of Innosilicon high-performance computing includes the world's top full-range high-end DDR series, the first Innolink™ Chiplet series compatible with UCIe standards, and the domestic leading SerDes (PCIe6/5) series, which can help customers optimize high- end Strict performance, power consumption, and cost targets on SoCs such as performance computing, AI, and graphics applications have greatly improved the efficiency of SoC R&D, reduced risks, and provided strong support for the upgrade of computing power requirements in the digital age.
▲ Industry-leading high-performance computing "three-piece" IP solution
The HPC IP "three-piece set" is the latest achievement of Innosilicon's 16 years of intensive cultivation of high-performance and high-reliability IP. It has three significant advantages: First, high-end performance. Regardless of DDR, Serdes or Chiplet, Innosilicon's performance is the world's leading , with the most complete interface coverage; the second is high-end process verification, high-end 10nm/8nm/7nm/6nm/5nm/3nm have been developed and verified and mass-produced by authorized customers; the third is cross-platform to ensure production safety, Innosilicon IP in TSMC /Samsung/GlobalFoundries/UMC/Intel/SMIC/Huali and other major foundries have all taped out and verified, and have authorized the mass production of billions of high-end SoC chips around the world, which can speed up SoC development and reduce risks.
The whole series of high-bandwidth DDR storage interface solutions break the memory wall
In terms of breaking through the memory wall technology, Innosilicon has the world's top full range of high-end DDR storage interface solutions. Not only took the lead in breaking through 10Gbps, mass-produced the world's fastest LPDDR5/5X Combo IP with advanced technology ; The rate is up to 7.2Gbps. All high-end DDR series IP can provide PHY and Controller overall solutions, and have been mass-produced and tested in advanced processes, fully support various JEDEC standards, in terms of performance and stability, size and power consumption, compatibility with more protocols, and application scenario optimization It is outstanding in terms of ease of use and integration, and can help breakthroughs in high-performance applications such as CPU/GPU/NPU high-performance computing, automotive autonomous driving, and mobile terminals.
▲The measured waveform of Innosilicon LPDDR5X (single-bit DQ up to 10Gbps) on a long-distance PCB board
Compatible with the UCIe Chiplet solution , breaking through the performance limit of a single chip
In response to the popular Chiplet technology, Innolink™ Chiplet, the first domestic cross-process and cross-package Chiplet connection solution-Innolink™ Chiplet, is the first to realize compatibility with two UCIe specifications (Innolink-B/C), helping chip design companies and system manufacturers to break through the single The limit of grain manufacturing and the performance bottleneck of a single chip have been successfully mass-produced on advanced technology. This solution not only supports standard packaging and advanced packaging, but also supports short-distance PCB scenarios. In various application scenarios, it has the advantages of low latency, low power consumption, high bandwidth density, and ultra-high cost performance. Covering D2D, C2C, B2B and other connection scenarios, it provides full-stack services such as packaging design, reliability verification, signal integrity analysis, DFT, thermal simulation, and test solutions.
▲Innolink™ Chiplet A/B/C implementation method
High-speed SerDes complete solution to open up the information highway
Innosilicon 32/56/64G SerDes complete solution has been at the international forefront in terms of speed, various interface standard types, silicon verification coverage and other important indicators, including PCIe6/5 (downward compatible with PCIe4/3/2), USB3.2/3.0, SATA, XAUI, SATA, RapidIO, CXL2.0, and the latest 112G SerDes are also under intensive development, with high compatibility, low cost, high performance, and high reliability, providing one-stop worry-free integration and flexible customization of Retimer Exchange chips with Switch for applications such as 5G communication, autonomous driving, artificial intelligence, big data storage, cloud computing, high-performance image media processing, and the Internet of Everything.
Right. Innosilicon does not make DDR5 wafers/chips.
DDR5 grade DRAM chips are supported by D1z node DRAM. CXMT has just recently achieved D1x level capability.
Not exactly. Not from a technical capability stand point.
CXMT had a later start than the Big 3 of DRAM. Recent year, CXMT's development pace has also been slower than the Big3, so the technical gap between CXMT and the leaders are getting bigger.
CXMT is barely migrating their DRAM process from D20 to D1x (18nm). They are still 'stuck' at DDR4/LPDDR4 DRAM chip. They are trying to catch the DRAM leaders all on D1a node, three generations ahead, by skipping nodes to jump directly to D1z node. But CXMT D1z development is not even near ready. The latest US Oct 7th sanction will not only slow down CXMT's current migration & capacity expansion plan centered around D1x but it will impact the timeline of D1z even more.
Even in memory down cycle, Moores law does not slow down. Despite Big3 reducing wafers starts per month, the migration from D1a towards D1b will not slow. March towards process node that yield more memory bit per wafer and improved performance will continue. When DRAM cycle bottoms out, we may find CXMT still stuck at D1x while the leaders roll out D1b, and we will be four generations behind the west.
So, US Oct 7th sanction DO have impact on domestic DRAM fabs. All predictions I read in SDF that US BIS sanction has minimum impact on China just doesn't reflect what we see in the real world, in our industry.
- CXMT technical roadmap has and will definitely be impacted.
- CXMT's wafer capacity expansion plan for D1x is also impacted.
- Without American WFE support and equipment, it's difficult for CXMT to continue expanding at the fast pace it was on.
CXMT could certainly use domestic etchers, deposition tools that are less reliable, slower, basically less efficient than industry tool of record. But using less efficient equipment with less efficient process node (higher $/memory bit) is not ideal. I'm sure CXMT would still have to continue its effort from a nationalistic agenda standpoint. But not reasonable for us to expect CXMT to
1. keep expanding and run 300K+ wafers per month of low efficient DRAM.
It's more reasonable to expect:
2. CXMT to continue developing advanced DRAM process and help domestic WFE suppliers improve at current 80K to 120K wafers per month.
No. SMIC accounts for 5% of foundry revenue NOT 5% of global chip sales.
You are correct. Currently, domestic WFE other than litho has been qualified only up to 28nm. Even then, these domestic equipment are still not at parity with industry's tools of record. We still have ways to go to improve domestic equipment's tool reliability, throughput, and yield.
SN1 expansion is basically completed. No more scanners needed and can't get access to American process equipment. Without American equipment, SN1 is unlikely to expand its wafer output; the bottleneck is limited by amount of American process equipment already purchased.
Your previous "predictions" on what SMIC's extra 1.6B CAPEX is for was not correct. Besides, like I said, the bottleneck at SN1 is not scanners. By the way, your prediction on NXT2050/2100 is too bullish. There aren't that many NXT2050 and there is no NXT2100 in China.
SN2 will not ramp for another year.
You think wrong, bud. Since SMIC could still buy ASML scanners, and you are aware and agree domestic non-litho equipment are at 28nm level.......American WFE is indeed the limiting factor for SMIC's SN1 & SN2.
With a full year of financial data, we will obviously see a great Y/Y revenue uptick. But, the revenue will definitely not reflect the full 35K wafer per month worth of revenue... Capacity in the beginning of the year is obviously lower than the second half of the year, so my guess we are more likely to see revenue reflecting 120K 14nm & 60K 7nm wafers for 2022.
There's quite a bit of equipment at 14 and and even lower though right? 28 is right where every equipment can hit yeah?
Can you explain why domestic WFE is qualified only for 28 nm when there's reports TSMC has qualified AMEC etchers for 5 nm?
There's also reports that NAURA equipment was used for 14 nm at least 2 years ago.
ACM Research is claiming that it has 20-14nm copper plating capability and they don't seem to be a company that can get away with too many bullshit claims since they supplied Samsung even 10 years ago.
You referenced deceptive marketing message.
For any given node, there is a spectrum of easy to complex process steps. Just because a tool is used for one of plethora of process steps for a given node doesn't make it a "5nm etcher" that could handle all etch steps.
I can't reveal too much, but let me ask you, have you any clue which process step tsmc uses AMEC's etcher for? Do you really believe its for the most critical layer or process step?
Only Chinese WFE suppliers go out of their way to attach a process node designation to their equipment. They do this to create buzz to hype up their true capabilities. We don't typically do that in our industry. Only the process engineers, we know which model is good enough for which process step, application, node combination.
In our industry, tools are advertised more so by application and its performance spec. We don't typically use a "node" as an adjective/description for the equipment.
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