@tphuang questioned the need for 7nm or better nodes in military applications like radar or EW.
I mentioned the Xilinx 7nm ACAP as an example of a COTS solution used in military applications: it happens to have a FPGA, but that’s only a part of its capabilities:
“Versal ACAPs combine scalar processing engines, adaptable hardware engines, intelligent engines with leading-edge memory and interfacing technologies to deliver powerful heterogeneous acceleration for any application beyond the capabilities of an FPGA.”
This is the sort of capability the US would like to stay ahead of China, which is why they are denying manufacturing tools to China for FinFETs or better. Reprogrammable FPGA have obvious benefits over ASICs: if you discover a bug down the road it is far cheaper to update an FPGA. If a new threat requires a different signal processing technique, it is again far cheaper to update the FPGA. This can even be done in-flight where a hardware swap or access to hardware may not be possible: think satellites.
According to the Microwave Journal, State-of-the-art fully digital cognitive radars require far more computing resources than possible from just a FPGA:
“New application areas add additional processing requirements. Cognitive radar applies artificial intelligence (AI) techniques to extract information about a target from a received signal, then uses the information to improve transmit frequency, waveform shape and pulse repetition frequency. Similarly, cognitive EW applies AI to identify patterns in the detected data to develop effective responses. Both cognitive radar and cognitive EW must execute their AI algorithms in near real-time. To do so, graphics processing units (GPUs) are added to RF processing, complementing the FPGAs that perform signal analysis and creation. Using many core processors is not the answer. While they can execute billions of instructions per second, they are not designed for low power consumption. They also need mixed-signal ICs and FPGAs for the RF interfaces, so a complete system requires a PCB.”
“Until recently, these multiple processing methods required distinct semiconductors, often assembled in a multi-board system. For RF applications, moving data from the ADC and DAC to centralized computing challenges data fidelity and latency. The current generation of converters are generating data bandwidths that overwhelm system interconnects, with transmission times that don’t support low latency radar and EW responses. This forces substantial data reduction before the central processor. To overcome these limitations, system architectures must move away from a centralized computing model to processing where the data is—at the tactical edge. Fortunately, new packaging technology helps solve that challenge.”
“RF edge processing requires multiple, tightly integrated functions working together to capture, analyze and manipulate a data stream in real time. Latency requirements favor ADCs and DACs that implement direct digital conversion. Efficient processing of the digital bit stream requires pipelined operations by some combination of FPGAs, GPUs and general-purpose processors. The components must connect via high bandwidth interconnects with low latency and be supplied with the required power. Everything must be assembled within a package small enough to be near the antenna.”
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