Chinese semiconductor industry
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PVD is a deposition method, EUV lithography is patterning. They are independent of each other. Whatever PVD technique you apply to the EUV patterned resist, you can apply to a DUV patterned resist.
I believe that the Dutch will eventually capitulate to US demands, despite it not being in their national interests to do so. It makes no economic sense and the Netherlands isn't interested in the containment of China, nor does it see China as a threat to its global and Asia-Pacific Dominance because the Netherlands in no way has that capability. Therefore, it does not make political sense for the Netherlands either...
Dutch Confirm Talks With US on Chipmaking-Gear Ban on China
- Dutch foreign minister says two countries discussed the issue
- US wants ASML to stop selling immersion lithography to China
Dutch Foreign Minister Wopke Hoekstra
Photographer: Peter Boer/Bloomberg
The Dutch foreign minister confirmed that the Netherlands and the US are holding discussions on blocking from selling to China technology used in making a large chunk of the world’s chips.
“What I can tell you is that it does make sense that you always liaise with friends when certain goods have broader strategic implications and ramifications across the globe,” Foreign Minister Wopke Hoekstra said in a wide-ranging interview in The Hague on Wednesday with a select group of journalists. “Of course you have conversations about that, and that we do.”
American officials are lobbying their Dutch counterparts to bar ASML from selling some of its older deep ultraviolet lithography, or DUV, systems, Bloomberg reported last week, citing people familiar with the matter. These machines are a generation behind cutting-edge but still the most common method in making certain less-advanced chips required by cars, phones, computers and even robots.
Washington is focused on banning sales of the most advanced type of DUV technology, immersion lithography machines, the people said.
The Dutch government, which faces pressure from US officials to expand an existing moratorium on the sale of such systems to the Asian nation, has yet to agree to any additional restrictions. China is the Netherlands’s third-biggest trade partner after Germany and Belgium.
ASML, on the other hand, opposes a ban on sales of DUV lithography equipment to Chinese customers because it is already a mature technology, Peter Wennink, the company’s chief executive officer, said earlier this year. Chinese-based facilities, run by either domestic or foreign companies, account for 14.7% of ASML’s total revenue in 2021, according to company disclosures and data compiled by Bloomberg.
ASML is the world’s top maker of lithography systems, machines that perform a crucial step in the process of creating semiconductors. ASML’s dominance of the market for that type of equipment means that further cutting China off from access to its products would undermine the Asian country’s ambitions to make itself more self-sufficient in production of the crucial electronic components.
Tensions have heightened in recent years between the US and China, the world top two economies. The US has accused China of human rights abuses in its far western Xinjiang region.
Commenting on the Dutch government’s stance on alleged human rights abuses in China, Hoekstra said he is “very worried about many of the news reports.”
“That’s been something I’ve been voicing and many of my colleagues have been voicing vis-a-vis the Chinese,” he said.
China has been accused of running a state-sponsored forced-labor program in Xinjiang under the guise of anti-poverty efforts, sending as many as 1 million Uyghurs to so-called re-education camps. China has repeatedly denied mistreatment of the Uyghurs and says crackdowns in Hong Kong are to prevent insurrection.
@Weaasel so bro what's your conclusion? will China IC be shattered or a renaissance in the making. I always believed that innovation and invention is a result of necessity, I can't forget what @BoraTas once posted in Quora, "Physic is the same in Amsterdam and Beijing" and from BYD CEO Wang Chuanfu "Chips are man made not by god". So I'm optimistic cause looking at the Chinese themselves , they seem confident and calm.
I'm sure there won't be any lack of Pottingers among Dutch government and industry policymakers
Using EUV in a non critical copper interconnexion layer will be some kind of a waste taking into consideration that LPP EUV machines wear out with use.
China will be able to make, within a few years, adequately functional 28 to 14nm DUV lithography machines free of any compromising foreign components. I am certainly not expert on lithography and IC semiconductor chip manufacturing processes, but I base this on the information that I have garnered from here and other sources... Even if the DUV or EUV is magical, China has its magicians too and the magicians are backed with the full weight of resources of the largest economy (certainly in term of PPP) on Earth...
Microelectronics has made progress in the structural design and simulation research of new vertical complementary field effect transistor (CFET)
Vertically stacked nanowire / nanosheet fully surrounded gate ( Gate All Around, GAA ) complementary field effect transistors ( Complementary Field Effect Transistor , CFET ), GAA devices of different conduction channel types ( N-FET and P-FET ) in vertical direction for high-density three-dimensional monolithic integration. Compared with the existing mainstream FinFET and horizontal GAA transistor integrated circuit technology, CFET breaks through the size limitation of the traditional N/P-FET coplanar layout spacing, and can reduce the size of the logic standard cell in the integrated circuit to 4-T ( Track ) height At the same time, it will reduce the area of SRAM cells by more than 40% , and will become a strong candidate for the innovative architecture of basic transistor devices in the generation of high-density, high-performance integrated circuit manufacturing technology below 3 nanometers.
Recently, the Yin Huaxiang/Wu Zhenhua research team of the IC Advanced Process Research and Development Center of the Institute of Microelectronics has comprehensively explored the device architecture advantages of CFETs using the industry's mainstream Design-Technology Co-optimization (DTCO) method, and proposed a new hybrid channel CFET ( Hybrid Channel Complementary ) . FET , HC-CFET ) structure design and integration scheme. This structure can be used on a single substrate, without the use of mixed crystal orientation technologies such as wafer bonding, using the high etching selectivity ratio of SiN x to SiO 2 , and through step-by-step channel topography etching, realizes N-FET and SiO 2. The co-optimization of high electron and hole mobility conductive channels is preferred for P-FETs , that is, N-FETs have a (100) channel surface orientation, and P-FETs have a (110) channel surface orientation, so that in the same projection Obtain the best device and circuit performance under the plane. The feasibility of the structural design and integration scheme has been verified by Virtual-FAB simulation. Further, all parasitic parameters are predicted through accurate numerical solution, and different CFETs are compared17 -stage ring oscillator and SRAM cell performance under the architecture . The results show that compared with the conventional vertically integrated Fin and vertically integrated nanosheet CFET structures ( MS-CFET and MB-CFET ), the new HC-CFET has the advantages of channel orientation and spatial layout, and exhibits higher operating frequency and Better noise margin window and great potential for highly scaled high-performance CMOS integrated circuits.
The result was recently published in the journal "Institute of Electrical and Electronics Engineers Journal of Electronic Devices" under the title "Investigation of Novel Hybrid Channel Complementary FET Scaling Beyond 3-nm Node From Device to Circuit" ( IEEE Transactions on Electron Devices 69, 3581 (2022). ), DOI: 10.1109/TED.2022.3176843 ), Luo Yanna, a doctoral student at the Institute of Microelectronics, is the first author of the article. Researcher Yin Huaxiang and Wu Zhenhua of the Institute of Microelectronics are the corresponding authors of this article. This research was supported by the " Strategic Key Research Program " of the Chinese Academy of Sciences , the National Natural Science Foundation of China, and the Science and Technology Program of the Beijing Municipal Science and Technology Commission. (Original link: )
The result was recently published in the journal "Institute of Electrical and Electronics Engineers Journal of Electronic Devices" under the title "Investigation of Novel Hybrid Channel Complementary FET Scaling Beyond 3-nm Node From Device to Circuit" ( IEEE Transactions on Electron Devices 69, 3581 (2022). ), DOI: 10.1109/TED.2022.3176843 ), Luo Yanna, a doctoral student at the Institute of Microelectronics, is the first author of the article. Researcher Yin Huaxiang and Wu Zhenhua of the Institute of Microelectronics are the corresponding authors of this article. This research was supported by the " Strategic Key Research Program " of the Chinese Academy of Sciences , the National Natural Science Foundation of China, and the Science and Technology Program of the Beijing Municipal Science and Technology Commission. (Original link: )
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