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@hvpc masterclass, hope all of you enjoy it as I do.
There are many different types of multiple-patterning. The one that most talked about is the litho-etch-litho-etch type. We called this LELE. This is actually a fairly simple and doable MP. But the process is complex.
For single exposure. (SE), you don't worry about how one line is patterned next to the next line because the line/space template is just a reduced image from the reticle/photomask (which you could safely assume the line line placement is accurate).
For LELE, one line is made with exposure A, and the next line is exposed with B. So any offset between exposure A & B (we called overlay) will need to be controlled. Scanners with improved MMO or matched machine overlay would be able to reduce the variability of pattern placement. But, you must monitor it to make sure the scanners did their job, right? Previously in SE, all you need to do is to monitor how the current exposure overlay to the previous layer on the bottom (one metrology step). With LELE, you'll need to monitor pattern overlay of exposureA-toB, exposureA-to-bottom, and exposure B-to-bottom. That's three metrology steps, three control loops.
So, more complex. But doable. Everyone could do this fairly successfully.
If we do what everyone here is claiming, just keep going with MP, let's say LELELE with exposure A, B, and C, besides, needing scanners to have perfect overlay all three times, the metrology step is now:
A-to-B, A-to-C, B-to-C, A-to-bottom, B-to-bottom, C-to-bottom....now, if we are talking about horizontal and vertical patterns on the same layer, the metrology steps doubles, too. With the extra complexity and needing to monitor, control all these potential source of error....man, it becomes difficult, cumbersome, and almost impossible to control. Yes, you may be able to get it right for a short while, but process do drift. Oh, I forgot, what I mentioned is if you keep everything on same scanners and etcher. If you starts to mix scanners and etchers, the number of SPC loop become even more complex,. It's easier to keep manufacturing of same batch of chip to one or two scanners. But not etchers. There are many etch chambers for each etch module....even in a lot of 20ish wafers, these has to split up between etch chambers. This lot of wafer needing to go through three different etch steps in a LELELE....my goodness, can imagine how you'd control the process? The metrology steps, the number of SPC, how/when to make correction would be nightmare.
So, it's a given that most feel LELE, or the other variant SelfAligningDoublePatterning (SADP) could be reasonably used and controlled. For logic guys, LELELE could be used, but mostly they use LELE to make smaller line/space pitch then use a third LE to cut out holes on the line to create separate features from a long space/line repeating pattern. For DRAM, SADP is okay, but everyone deemed SAQP (quadruple patterning) to be almost impossible
Because the SAxP type multiple patterning is done not with scanners. The line pitch splitting is done with deposition and etch. Since these cheaper, less accurate tools have much worse precision or repeatability compared to the scanners, the accuracy/precision correction needed in the multiple patterning could not be applied. So the error tolerance or process window of SAxP is a lot worse than the LELE type. This is why the LEx type MP could be than to LE3, but SAxP type is mostly kept at SA2P. The only time SAQP could be attempted is if the pattern is just ONLY line/space pattern (1D pattern).
So, as you see, what could be done in theory on simple 1D feature, only yield for a wafer/lot is a lot different in the actual use case where complex 2D pattern, high volume control, high yield, etc. is needed.
What most non-industry expert may be exposed to are simple tutorial online or in publication to explain concepts of multiple patterning. Most people are not even aware what it is like in the real world or in a HVM setting. I would say most if not all scholars do not understand the actual complexity unless they have first-hand experience,. and I can tell you there are very few of us lithography guys that have actual experience with advanced manufacturing of leading edge logic wafers.
