Again, if it needs the level of accuracy of FE iline scanners, our industry would've simply take a FE 4x iline scanner and put in a 2x reduction lens and be done with. But why wasn't this done? smaller "nm" come at higher tool price, which wouldn't be ideal for even advanced packaging litho tool. The biggest challenge of advanced packaging is trying to keep the cost under control and closer to the traditional packaging.
TSV HAR etch is still not as difficult. Look at price delta between TSV etcher and CCP/ICP etcher. Yes, HAR not easy, but DRAM capacitor is also relatively high aspect ratio (not as high as TSV) but much smaller in size and much denser. Different challenge, but again, difficulty is rewarded with higher tool price. The price is supporting evidence of the degree of difficulty.
TSV ~5um
DRAM storage node: <40nm now
As "advanced" as packaging go, it's still operates in a completely different physical size range. Here's a visual to show TSV vs. HAR DRAM capacitors (which you can't even see on the stack of DRAM chips on top because it's too small). The $ spent on FE vs BE is also very telling in which is more complex. Again, I'm not bashing and saying BE flow is not difficult or challenging, I'm just saying it's less so compared to the amount of work/innovation required to meet FE requirements.
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