What would happen if it were with newer process node of 14nm and 7nm and with Chinese design? Would the performance become 3x or 5x better ?
when you get to that level you have quite a bit of dark silicon (unused transistors) due to thermal overload if all transistors were used at once, which is why mere die shrinks are hitting the wall. remember back 20 years ago that clock speeding up was the way to add speed but then it stopped working, then it was die shrinks to put multiple cores on 1 die but now it stopped working too, then it was SoC to put peripherals on the same die as well.
in terms of process you had to move from planar transistor to finFET for further die shrinks, you had to use metal gate instead of polySi gate, you had to use high-k instead of silicon dioxide insulator, etc. Beyond just lithography, the entire chemical processing of the chip changed. it's a paradigm shift.
now you're at the limit, hitting shrinking return on investment, and need a new paradigm. the 3D packaging integration is the new paradigm. so mere die shrink in this case may or may not increase performance but it won't be 3x-5x.