Chinese semiconductor thread II

PopularScience

PopularScience

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visitant said:
3D stacking is not new; it has already been implemented in memory chips and TSMC's technology roadmap, but Huawei has clearly gone further in this direction.
Kirin2026 achieved performance that would normally require two or three generations of advanced processes thanks to its new architecture. As the conference presentation stated, increasing transistor density was not the goal from the beginning.

Assuming this roadmap holds true, the high investment required for new manufacturing processes is indeed overwhelming even for TSMC, this seems to suggest that the chip industry is returning to an era where vertical integration is needed from initial design/EDA software to the production steps. Does this mean that companies like Intel, Samsung, and Huawei will gain an increasing competitive advantage in the chip industry?

I'm not a semiconductor professional, are there any industry insiders here to share their views?
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real and fake 3d

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jx191

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latenlazy said:
EUV has to happen a few years before takeover for this roadmap to pan out because convergence doesn’t just require EUV but that Huawei is matching TSMC performance at the takeover point, which by 2030 should be when TSMC is reaching a 1 nm process node. Just getting EUV doesn’t automatically vault Huawei to a 1nm equivalent performance.
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Just looking over this again, what do you mean by "convergence" and "takeover?"

Are you saying that EUV must be in production before 2030? That would make sense considering it will take a while for the systems to be fully integrated and functional.
 
sunnymaxi

sunnymaxi

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tokenanalyst said:
Is way more complicated than that. A good analogy would be let suppose you live in a city and you have a friend that you visit with some frequency but that friend lives 1Km away so you have to travel a lot, now let suppose that in order to shorten the travel time and save fuel I decide to build a second floor over your house and move your friend there so the travel distance and time is shorten from 1km to 3 meters, let suppose I do that across the city with a lot of people, fuel consumption is reduced and with added bonus of more empty space for more people. This is different and more complicated than 3DNAND and HBM.

The issue is that the entire industry is designed for "planar" floor planning, the PDKs are made for traditional ICs were geometrical scaling is the norm. Huawei has to from zero develop the entire toolset from the TCAD simulations way down to the physical verification to take into account this "time constant" in the design. Apart from reducing unwanted capacitance, inductance and heat.

But logic folding is only the beginning, the proof of concept, they this will be implemented at ALL levels of the chip fabrication from transistor level to system level. They are not going to stop geometrical scaling but slow it down in favor of time scaling.
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i have seen very good 3D stacking semiconductor design with regular 2D design. perfectly fit with your city example.

HJPtIpjaEAAKatf.jpg

the most interest aspect of this new architecture is, the amount of innovation in materials, new Bonding equipment, a complete 3D EDA stack and other different tools is mind boggling. and of course Huawei have worked with domestic tools makers in order to provide them feedback what kind of tools they wanted. basically entire ecosystem innovated around this new architecture.

most likely they have separate assembly line for these chips.
 
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gaussgun

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Memory Chip Giant CXMT Heads for China’s Biggest IPO Since 2022

Memory chip maker ChangXin Memory Technologies Inc. has received approval from the Shanghai Stock Exchange for an initial public offering that's on track to be the biggest in mainland China since 2022, in a milestone for one of the key technologies of the artificial intelligence buildout.

The company plans to raise at least 29.5 billion yuan ($4.3 billion) on the chip- heavy STAR Board, offering no less than 10% of its shares, according to its prospectus. The size could rise to more than $5 billion if the over-allotment options is exercised.

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henrik

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gaussgun said:
Memory Chip Giant CXMT Heads for China’s Biggest IPO Since 2022

Memory chip maker ChangXin Memory Technologies Inc. has received approval from the Shanghai Stock Exchange for an initial public offering that's on track to be the biggest in mainland China since 2022, in a milestone for one of the key technologies of the artificial intelligence buildout.

The company plans to raise at least 29.5 billion yuan ($4.3 billion) on the chip- heavy STAR Board, offering no less than 10% of its shares, according to its prospectus. The size could rise to more than $5 billion if the over-allotment options is exercised.

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Considering that CXMT 2026Q1 net profit is 24.76 billion RMB (~$3.6 billion USD), the whole company market cap at US $50B is very low valuation. The next phase of capacitiy will come online, so profits will double next year.
 
tphuang

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tokenanalyst said:
Is way more complicated than that. A good analogy would be let suppose you live in a city and you have a friend that you visit with some frequency but that friend lives 1Km away so you have to travel a lot, now let suppose that in order to shorten the travel time and save fuel I decide to build a second floor over your house and move your friend there so the travel distance and time is shorten from 1km to 3 meters, let suppose I do that across the city with a lot of people, fuel consumption is reduced and with added bonus of more empty space for more people. This is different and more complicated than 3DNAND and HBM.

The issue is that the entire industry is designed for "planar" floor planning, the PDKs are made for traditional ICs were geometrical scaling is the norm. Huawei has to from zero develop the entire toolset from the TCAD simulations way down to the physical verification to take into account this "time constant" in the design. Apart from reducing unwanted capacitance, inductance and heat.

But logic folding is only the beginning, the proof of concept, they this will be implemented at ALL levels of the chip fabrication from transistor level to system level. They are not going to stop geometrical scaling but slow it down in favor of time scaling.
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Keep in mind that 3D NAND and HBM are not the same.

3D NAND are still 1 die and HBM are multiple dies stacked together.

3D DRAM and 3D NAND are both logical comparisons to 3D IC/Logic Folding here because essentially it's all one die, so all the layers should be designed as part of a single unit.

In HBM or classical 3D Packaging, you are stacking together multiple dies with TSV interposer (or whatever else). So they don't have the same EDA requirement, layer spacing requirements. If your layers are too far apart, then logic folding doesn't work for 3D IC.
 
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