Chinese semiconductor thread II
- Thread starter vincent
- Start date
Kirin 2026 TSMC N3P level density? would be interesting to see
I have no idea what is being talked about here. Can you please explain?
Also, where are you getting these slides from?
But you are comparing density of a 2D chip with the density of a 3D chip. Very different beasts. Don't know if they can be compared. Maybe power performance etc. needs to be taken into account too.
I’ll have to do a bit more reading to be sure and if someone has access to some technical papers it would help sort through what Huawei is proposing in more specific terms but so far from what I can gather “Tau scaling” is a proposal to essentially change the performance rubric from transistor density by area to signal (aka switching) density by time. It seems they’re shifting their design optimization paradigm toward increasing instruction frequency per unit of energy consumption rather than effective transistor counts within a die area, and their proposal seems to include optimization for parameters not just at the die level but the systems level since a “signal density and efficiency” metric doesn’t just involve what goes on with the operations happening on the transistor or die level but holistic operations across a whole computing system.
note the big increase in year 2030. I think this is the timeline for EUV.
EUV has to happen a few years before takeover for this roadmap to pan out because convergence doesn’t just require EUV but that Huawei is matching TSMC performance at the takeover point, which by 2030 should be when TSMC is reaching a 1 nm process node. Just getting EUV doesn’t automatically vault Huawei to a 1nm equivalent performance.
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They are going to co-optimize from the transistor level to system level. That means they are going all in process optimization, new materials and tools. ALD of new materials, Epitaxial materials, ALE, implantation and so on. Maybe is were all those SiCarrier tools are going in.
Yes but it’s about more than just co-optimization. Sounds like they’re also proposing different optimization heuristics for die layout design and transistor architecture. On die transistor density itself may be deprecated from being the primary priority in design iterations. In a hypothetical sense if they can get to equivalent frequency of operations with a lower density on die design at equivalent energy budget as a higher density on die design that would be considered equivalent performance based on their tau scaling principles.
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