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Chinese semiconductor thread II
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A Wafer-Level Stacking Scheme Based on Hybrid Etching and Low-Temperature Bonding for High-Performance MEMS Devices
Abstract
Silicon micromachining serves as the foundational enabling technology for high-precision MEMS inertial sensors. However, the relentless pursuit of enhanced sensitivity and multi-functionality in emerging applications encounters a fundamental bottleneck when confined to two-dimensional scaling. The evolution toward complex three-dimensional (3D) stacking architectures is an inevitable trajectory for devices including MEMS inertial sensors, yet performance is constrained by the limitations of conventional processes in fabricating and integrating intricate 3D hollow structures. Specifically, uniformity in large-area deep silicon etching, structural integrity of convex corners in wet etching, and residual stress induced by multi-layer wafer bonding have emerged as critical, shared challenges. To address these issues, this paper proposes a triple-layer wafer-level stacking scheme that synergistically combines wet/dry hybrid etching with low-temperature adhesive bonding. This stacking scheme incorporates an innovative linear compensation model for wet-etched convex corners, enabling high-precision fabrication of complex corner structures under deep etching conditions. Furthermore, a collaborative strategy involving temporary bonding and plasma flow-field optimization improves the uniformity and integrity of dry etching for large perforated structures. A low-temperature triple-layer wafer-level stacking process is developed, encompassing precise adhesive dispensing, optical alignment, and a stepped low-temperature curing profile, thereby achieving highly symmetric 3D integration with controlled adhesive distribution. The efficacy of this stacking scheme is validated through the fabrication of a symmetrically stacked triple-layer MOEMS accelerometer sensing element. Test results demonstrate a noise floor as low as 0.40 µg/√Hz and a bias instability of 1.81 µg over 10 min. Compared with a double-layer counterpart, improved performance is obtained. The wafer-level stacking scheme established in this work not only provides a viable pathway for pushing the manufacturing limits of high-precision inertial devices but also offers a generic methodology for tackling complex hollow structure formation and low-temperature integration, holding referential value for broader applications in high-precision 3D microsystems.
Development of a Bionic Bistable Compliant Mechanism for the LDI (Laser Direct Imaging) Machine
Abstract
Rigid mechanisms (RMs) are widely adopted in the vision-based measurement (VBM) system of laser direct imaging (LDI) machines. Constant-stiffness compliant mechanisms (CMs) improve the performance of traditional RMs. Unfortunately, constant-stiffness CMs still exhibit high energy consumption and limited adaptability during fast focusing. Inspired by the hierarchical structure and mechanical behavior of ligaments and tendons, this paper proposes a bionic bistable compliant mechanism (BBCM) to replace constant-stiffness CMs. The BBCM exhibits dynamic stiffness characteristics throughout the focusing stroke, with low stiffness in the transition phase to reduce energy consumption during rapid focusing and high local stiffness near the stable positions to maintain focusing stability. A numerical model is established to analyze the variable-stiffness and bistable characteristics of the proposed BBCM. Prototype tests demonstrate the bistable response, dynamic feasibility, and energy-saving potential of the mechanism. Under the tested camera-loaded flying-shot condition, compared with the constant-stiffness CM, the BBCM reduces electrical and mechanical energy consumption by 12.37% and 9.74%, respectively. The target recognition results indicate that the BBCM-based system maintains comparable visual measurement performance. These results demonstrate that the proposed BBCM provides a feasible mechanism-level solution for energy-efficient dual-position focusing in LDI machines.
Dual-Wavelength Optical Triangulation System for Focus Metrology in 350 nm Lithography
Abstract
Thin-film interference in photoresist stacks can become a significant source of uncertainty in lithographic focus metrology, particularly when high measurement stability is required. To evaluate this effect, a Fresnel-based multilayer reflection model is used to analyze the optical response of the resist stack and to guide the selection of dual-wavelength illumination. On this basis, a dual-wavelength optical triangulation system is developed for focus metrology in 350 nm lithography, with signal acquisition performed by a linear charge-coupled device (LCCD). Rather than improving precision by reducing detector pitch, the system employs a two-stage sub-pixel localization strategy in which template matching provides coarse spot localization and weighted centroid interpolation refines the final position within localized calculation windows, keeping the computational cost manageable. A covariance-based uncertainty analysis predicts a total root-mean-square uncertainty of 27.23 nm. Prototype experiments were performed on a bare silicon wafer to establish the intrinsic performance of the instrument before introducing process-dependent optical effects. Under these conditions, the system achieved a vertical resolution of 10 nm, a repeatability of 35 nm, and a stability of 13.16 nm. The additional uncertainty expected under resist-coated-wafer conditions was assessed separately through the thin-film model. These results verify the baseline capability of the proposed system and support the feasibility of the dual-wavelength strategy for focus metrology in 350 nm lithography.
3D stacking is not new; it has already been implemented in memory chips and TSMC's technology roadmap, but Huawei has clearly gone further in this direction.
Kirin2026 achieved performance that would normally require two or three generations of advanced processes thanks to its new architecture. As the conference presentation stated, increasing transistor density was not the goal from the beginning.
Assuming this roadmap holds true, the high investment required for new manufacturing processes is indeed overwhelming even for TSMC, this seems to suggest that the chip industry is returning to an era where vertical integration is needed from initial design/EDA software to the production steps. Does this mean that companies like Intel, Samsung, and Huawei will gain an increasing competitive advantage in the chip industry?
I'm not a semiconductor professional, are there any industry insiders here to share their views?
Kirin2026 achieved performance that would normally require two or three generations of advanced processes thanks to its new architecture. As the conference presentation stated, increasing transistor density was not the goal from the beginning.
Assuming this roadmap holds true, the high investment required for new manufacturing processes is indeed overwhelming even for TSMC, this seems to suggest that the chip industry is returning to an era where vertical integration is needed from initial design/EDA software to the production steps. Does this mean that companies like Intel, Samsung, and Huawei will gain an increasing competitive advantage in the chip industry?
I'm not a semiconductor professional, are there any industry insiders here to share their views?
It's more precise to describe what Huawei did as less about 3D stacking and more about using the 3D design space to optimize circuit efficiencies that then let them fit in a lot more transistors vertically with minimal thermal and power draw penalties.
broadsword
Brigadier
Is way more complicated than that. A good analogy would be let suppose you live in a city and you have a friend that you visit with some frequency but that friend lives 1Km away so you have to travel a lot, now let suppose that in order to shorten the travel time and save fuel I decide to build a second floor over your house and move your friend there so the travel distance and time is shorten from 1km to 3 meters, let suppose I do that across the city with a lot of people, fuel consumption is reduced and with added bonus of more empty space for more people. This is different and more complicated than 3DNAND and HBM.
The issue is that the entire industry is designed for "planar" floor planning, the PDKs are made for traditional ICs were geometrical scaling is the norm. Huawei has to from zero develop the entire toolset from the TCAD simulations way down to the physical verification to take into account this "time constant" in the design. Apart from reducing unwanted capacitance, inductance and heat.
But logic folding is only the beginning, the proof of concept, they this will be implemented at ALL levels of the chip fabrication from transistor level to system level. They are not going to stop geometrical scaling but slow it down in favor of time scaling.