Co-Design of a Optimized De-Embedding TSV Test Structure and a High-Density Surrounding DTCAP for 3DIC Power-Signal Integrity
Abstract:
This paper presents a co-design method for 3D integrated circuits (3DICs), synergistically integrating a high-density deep trench capacitor (DTC) with a through-silicon via (TSV) test structure that uses optimized de-embedding techniques. This integration enhances both power and signal integrity. The DTC features an array structure built with high-κ dielectrics and multi-layer electrodes. It achieves an ultra-high capacitance density, by optimizing the trench width. This represents a 20% improvement over conventional designs. A dedicated TSV de-embedding test structure was also designed to extract TSV parasitic parameters, enabling accurate extraction of TSV parasitic parameters within a 5% error margin. Joint electromagnetic simulations were also performed. The results show that after integration with the TSV, the DTC's resonant frequency shifts from 2.5 GHz down to 415 MHz. This shift is caused by an increase in series parasitic inductance. The change can significantly impact power delivery network (PDN) impedance and simultaneous switching noise (SSN). This work provides valuable insights for applications in high-performance computing (HPC) and radio-frequency (RF) 3DICs.
