my latest on Tau Scaling of AI chip and Atlas/Ascend after reading this slide
Chinese semiconductor thread II
- Thread starter vincent
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my latest on Tau Scaling of AI chip and Atlas/Ascend after reading this slide
ChipVision releases the world's smallest 0.13-inch LCoS chip
On June 4th, Nanjing Chipvision announced the Tianmu 80, the industry's smallest LCoS silicon-based microdisplay chip. With a display size of only 0.13 inches (about the size of a grain of rice), this chip has broken the global record for the smallest microdisplay hardware.
The chip has a resolution of 640×480 and a pixel size of only 4.0×4.0μm. It adopts reflective LCoS single-chip full-color display technology and supports high-speed serial interfaces such as MIPI and LVDS.
Leveraging the ultra-high pixel density brought by the 4.0μm pixel specification, this chip can eliminate the screen-door effect in displays, providing key technical support for lightweight consumer display terminals.
Meanwhile, this chip achieves a high aperture ratio within a single pixel of 4μm, overcoming the core challenges of light efficiency, brightness, and contrast.
GigaDevice and NIO Reach Strategic Cooperation
GigaDevice and NIO have formally established a comprehensive strategic partnership focused on accelerating innovation within the automotive chip sector. This collaboration aims to deepen localization across the entire vehicle industry chain by integrating GigaDevice's robust semiconductor capabilities with NIO's expertise in intelligent electric vehicle development. Specifically, GigaDevice will leverage its mature R&D technology and certifications in core components such as memory chips, MCUs, and sensors, while NIO provides extensive real-world application data from areas like advanced driving and intelligent cockpits. Together, they intend to break down barriers between upstream chip research and downstream vehicle deployment, creating an integrated system that customizes high-performance domestic chips for critical scenarios including autonomous driving and vehicle electronics control.
Beyond a simple supply relationship, this alliance represents a long-term commitment to jointly define specifications, conduct co-development, test adaptability, and manage mass production to address industry bottlenecks in compatibility and iteration speed. For NIO, this partnership is expected to significantly enhance the domestic localization rate of core components, shorten product development cycles, and bolster its competitive edge through superior hardware performance. On a broader industrial scale, the cooperation signifies a decisive move toward reducing reliance on foreign manufacturers and fostering an independent ecosystem for high-end automotive semiconductors in China. By driving accelerated substitution and collaborative innovation between leading domestic chipmakers and EV brands, this initiative injects substantial technological momentum into the quality development of the nation's new energy vehicle industry.
Accelerating the Modified Born Series Using the Beam Propagation Method for EUV Lithography
Mask optimization (MO) is indispensable in extreme ultraviolet lithography (EUVL) due to significant thick-mask effects, in which an accurate mask model is fundamental. The mask model is invoked repeatedly in MO, making its computational speed a critical factor. Besides, the speed of the mask model is also critical for the increasingly adopted deep learning models, since their training demands the in-time generation of massive, configuration-specific data. To meet both challenges, we propose a method to accelerate the modified Born seriesbased EUVL mask model. Specifically, the beam propagation method provides an initial condition for the modified Born series, which lowers the iteration count and thus the total simulation time. The proposed method achieves runtime reductions of approximately 47.56% in a typical EUVL MO example and 37.58% in data generation, respectively.
Novel “S-Cut” Flows for Highly Uniform Multi-Tier Integrated Oxide Semiconductor DRAM
ChangXin Memory Technologies
Beijing Superstring Academy of Memory Technology
Beijing Superstring Academy of Memory Technology
Abstract:
We propose “S-Cut” (S-shaped Cut) integration flows to achieve five-tier oxide-based DRAM transistors and a 64 × 256 array without parasitic channels on a 12-inch manufacturing line. Two “S-Cut” approaches are investigated: the “outer-cut” flow, which removes the parasitic channel from the bit line direction, and the “inner-cut” flow, which removes it from inside the transistor hole. After flow and process optimization, including bit line/oxide channel contact optimization and common bit line/staircase parasitic resistance reduction, the “inner-cut” flow demonstrates good uniformity both across the five tiers and across the entire 12-inch wafer. The Ion of a single transistor reaches 77μA/μm, the Ioff is less than 1×10−18A/cell, and I-V hysteresis is nearly 0 mV. Remarkably, the uniformity (Std./Mean across the 12-inch wafer) of Vth among the five tiers ranges from 0.10 to 0.22, while that of Ion ranges from 0.14 to 0.51. The survival ratio for both Vth and Ion exceeds 90%. This study is the first to demonstrate that “S-Cut” is a promising integration pathway for oxide-based multi-tier DRAM architectures on a 12-inch manufacturing line.