Chinese semiconductor thread II
- Thread starter vincent
- Start date
That is interesting.
So the current 2-layer chip has a similar transistor density to TSMC N5.
That implies each layer is half the area of the single TSMC layer.
And with half the layer area, that means twice as many dies on a wafer.
So for a given number of wafer defects, the number of affected dies would typically halve?
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Then the with 3-layer, the transistor density reaches TSMC N3 levels.
If they can get to 4-layers, that implies transistor density almost reaches TSMC N2 level.
But the Huawei roadmap projects reaching TSMC N1.5 level by 2031, and they say this will be done without EUV lithography.
But Chinese EUV lithography machines might be ready in 2030?
It explains why Huawei is confident they can keep up, and why Nividia was so vocal that continued American semiconductor sanctions on China are going to fail.
This is really a problem of EDA deal with assuming the bonding of the two dies (or wafers) are executed using existing bonding method? Huawei is confident that the western EDA companies are not able to do the same thing within a few years, hence making the announcement?
Tau Scaling revealing is so unlike Huawei. For years since being sanctioned, Huawei refused to even release specifications for their AP processors. But this is an all-in, open marketing campaign with ads in x.com, speeches in leading technical seminars, press releases and even never-before interviews with key executives like "Chip Queen" He Tingbo. The only parallel I can see is the heavy promotion of polar codes during the 5G standard race which sealed Huawei as the leading telecommunications company. This is something really big, is ready and will have huge impact in the years ahead.
They have something bigger to announce soon. That is why they have to announce this first. It was like announcing the J-35 first, before the test flights for J-36 and J-50 were revealed.
This reveal shift focus from lithography machine to CMP, thinning, hybrid bonding machines and EDA.
ChipletTech has successfully developed chip bonding equipment, filling a domestic gap with nanometer-level precision.
Xu Zhoulong used an analogy: the diameter of a human hair is about 100 micrometers, while the stacking and positioning accuracy of ChipletTech's equipment can reach 30 nanometers, which is only 1/3000 of the diameter of a human hair. The motion control accuracy has even broken through to 10 nanometers, which is equivalent to 1/10000 of the diameter of a human hair.
Xu Zhoulong used an analogy: the diameter of a human hair is about 100 micrometers, while the stacking and positioning accuracy of ChipletTech's equipment can reach 30 nanometers, which is only 1/3000 of the diameter of a human hair. The motion control accuracy has even broken through to 10 nanometers, which is equivalent to 1/10000 of the diameter of a human hair.
But this logic folding can still be used on chips fabbed via euv. I am not sure why there is a shift of focus.
sweet spot for 3d folding is 5 ~7nm.
Why is it?