Chinese semiconductor thread II

tokenanalyst

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Keep in mind that 3D NAND and HBM are not the same.

3D NAND are still 1 die and HBM are multiple dies stacked together.

3D DRAM and 3D NAND are both logical comparisons to 3D IC/Logic Folding here because essentially it's all one die, so all the layers should be designed as part of a single unit.

In HBM or classical 3D Packaging, you are stacking together multiple dies with TSV interposer (or whatever else). So they don't have the same EDA requirement, layer spacing requirements. If your layers are too far apart, then logic folding doesn't work for 3D IC.
Yes, 3D-NAND is a real 3D circuit but still a stack because the vertical linearity. HBM is just die stacking. 3D Folding have to designed to advantage of the verticality. I think will start with hybrid bonding but will eventually move to process manufacturing.
 

tokenanalyst

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Xilian Optoelectronics completes hundreds of millions of yuan in Series B5 financing to strengthen its global layout of silicon photonics chips.​


On May 26, 2026, according to Cailian Press, Changzhou Xilian Optoelectronics Technology Co., Ltd. (hereinafter referred to as "Xilian Optoelectronics") recently completed a B5 round of financing worth hundreds of millions of RMB. This round of financing was led by Yongxin Ark, with participation from several well-known institutions including industrial capital, leading RMB funds, and leading USD funds.

Xilian Optoelectronics was established on July 20, 2020, with Li Xiaojun as its legal representative. It is a high-tech enterprise focusing on the research and development of core technologies for fully integrated silicon photonics chips. Founded by senior experts in the semiconductor and silicon photonics fields, the company is committed to building a silicon photonics technology platform, with products targeting fields such as AI computing, 5G communication, data centers, and autonomous driving.

The company headquarters has relocated several times: initially located in Suzhou, it officially moved to Wujin District, Changzhou, Jiangsu Province in April 2025, settling in Wujin National High-tech Industrial Development Zone. In October 2021, Xilian Optoelectronics completed the acquisition of 100% equity of German Sicoya GmbH, establishing two major R&D centers in Shanghai and Berlin, forming a global collaborative innovation R&D system.

In terms of technology, the company has mastered the core capabilities of the entire silicon photonics chain, covering chip design, tape-out process, wafer testing, and optical engine development; it owns more than 100 core patents, and its full range of silicon photonics chips from 400G and 800G to 1.6T have been supplied in batches to leading customers at home and abroad.

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tokenanalyst

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Bayi Space: Photoresist resin has achieved large-scale production, verified and put into mass production at wafer fabs.​

On May 26, Bayi Space issued an investor relations activity record announcement, stating that the company's photoresist resin has taken the lead in achieving large-scale production, serving leading photoresist customers, and has been verified and mass-produced in wafer fabs.

Thanks to successful customer certification and order volume increases, capacity utilization has improved and costs have continued to decline. However, the company is currently increasing its investment in resin material R&D and is actively promoting the construction of larger-scale mass production lines, which is expected to lead to an increase in various expenses. The company hopes to achieve profitability in its photoresist resin business as soon as possible by further increasing the scale of supply in the future.

The company has the capability to develop and produce a full range of high-end semiconductor photoresist (KrF) resins and has cooperated with several leading photoresist manufacturers. Currently, several resin products have been mass-produced and delivered to customers, and both product quality and order volume have improved, achieving stable shipments at the ton level.

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tokenanalyst

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Huada Jiutian launches Argus 3DIC physical verification platform, filling the gap in high-end 3DIC design tools in China.​


On May 25, 2026, leading domestic EDA company Huada Jiutian officially launched the Argus 3DIC physical verification platform. This launch makes Huada Jiutian the only provider in China with full-process EDA capabilities for 3DIC design and verification, successfully filling a critical gap in the domestic high-end 3D chip design tool market and breaking the long-standing monopoly of overseas EDA giants.

The Argus platform is an end-to-end solution for 2.5D/3D heterogeneous integrated packaging, featuring several major technical breakthroughs:​
  • Unprecedented Speed: Using proprietary "3D data weaving" technology, the platform verifies full 3D data without needing to split the die. This makes it 5 times faster than traditional overseas tools, shrinking end-to-end verification cycles from two weeks down to just 1-2 days.​
  • Advanced Diagnostics: It overcomes complex challenges in 3D signal integrity and multi-chip thermal simulation. Crucially, it accurately detects fatal flaws like inter-die antenna effects that traditional tools miss, significantly boosting chip yield and reliability.​
  • High Capacity: The platform supports the high-performance inspection of tens of millions of HB (hybrid bonding) stacks, catering to the massive scale required by modern AI and High-Performance Computing (HPC) chips.​
Previously, Chinese chipmakers relied entirely on expensive, imported tools for 2.5D/3D packaging verification. Argus provides a secure, independent alternative, mitigating supply chain risks and lowering R&D costs. As the global semiconductor industry pivots toward advanced packaging to bypass the physical limits of Moore's Law, Argus provides the necessary foundational software for China's domestic chipmakers. It will accelerate the deployment of homegrown advanced packaging technologies across the AI, advanced storage, automotive electronics, and HPC sectors.

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sunnymaxi

Colonel
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What is the source for this?
its from Zheng Jun, the CTO of the Huawei Financial System Department.

Zheng Jun said:​

“Chips are developing based on Tao (τ) Law have been applied to the Huawei Mate 90 model, achieving a top-tier process level close to 3nm.”

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Mate90 is going to release either in September or October this year.
 

tokenanalyst

Lieutenant General
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Proof of concept​

Holographic EUV Lithography at 40 nm Resolution​

Abstract.​

Extreme ultraviolet (EUV) lithography is the cornerstone of the fabrication ofadvanced integrated circuits at the 7-nm node and beyond, but its reliance onmulti-element reflective projection optics makes it inaccessible for small-scaleresearch and prototyping. EUV interference lithography (EUV-IL) provides alensless alternative but is intrinsically restricted to periodic structures. Here we demonstrate EUV holographic lithography (EUV-HL) as a lensless route to arbitrary, non-periodic, curvilinear patterning at the EUV wavelength of 13.5 nm.We introduce an inverse-design framework for computer-generated holograms that captures the dominant physical effects of EUV mask diffraction within a shift-invariant convolution model that is tractable for full mask layouts. Using this framework, we design and fabricate transmissive holographic masks by direct-write electron-beam lithography in hydrogen silsesquioxane, expose them with synchrotron-generated EUV radiation, and print target layouts with critical dimensions down to 40 nm, nearly an order of magnitude finer than the previous state of the art in EUV-HL. The demonstrated combination of sub-50 nm resolution, curvilinear design freedom, and a lensless optical setup establishes EUV-HL as a uniquely flexible tool for nanostructure prototyping at EUV wavelengths,and provides a natural pathway to non-periodic pattern prototyping at beyond-EUV (BEUV) wavelengths, which is currently inaccessible to interference-based methods.

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tokenanalyst

Lieutenant General
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its from Zheng Jun, the CTO of the Huawei Financial System Department.

Zheng Jun said:​

“Chips are developing based on Tao (τ) Law have been applied to the Huawei Mate 90 model, achieving a top-tier process level close to 3nm.”

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Mate90 is going to release either in September or October this year.
The teardown will be quite interesting.
 

jli88

Junior Member
Registered Member
its from Zheng Jun, the CTO of the Huawei Financial System Department.

Zheng Jun said:​

“Chips are developing based on Tao (τ) Law have been applied to the Huawei Mate 90 model, achieving a top-tier process level close to 3nm.”

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Mate90 is going to release either in September or October this year.

They have created quite a buzz for Mate90 and its teardown then. Looking forward to techinsights teardown.
 
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