Chinese semiconductor thread II

[tokenanalyst]

AMEC aims to achieve a market share of over 70% in advanced packaging equipment.​

Yin Zhiyao, chairman of Advanced Micro-Fabrication Equipment Inc. (AMEC), recently stated that the company has the capability to manufacture the most advanced semiconductor equipment. He outlined the company's development goals for the next five years: to strive to cover more than 60% of high-end key equipment for integrated circuits and more than 70% of advanced packaging equipment within five years.

Founded in May 2004 by Yin Zhiyao, AMEC successfully developed its own etching machine in just three years. Against the backdrop of US sanctions against my country's high-tech sector, AMEC is becoming a vital force in the domestic substitution of semiconductor equipment in China.

According to CCTV, Yin Zhiyao explained that before AMEC decided to enter the field of large flat panel equipment for semiconductor microfabrication, almost all of the equipment for about 17 processes in this field relied on imports. Based on past experience, developing such equipment typically takes 3 to 7 years. However, AMEC completed the equipment development in just 12 months, met the customer's next-generation product requirements in less than 4 months, and achieved online production and verification in 18 months.

Yin Zhiyao emphasized that AMEC currently possesses the capability to manufacture state-of-the-art equipment. However, he also admitted that many domestic customers still hold the preconceived notion that "foreign equipment is better," and appealed to domestic customers to give local equipment manufacturers more opportunities for trial and verification.

According to its recent financial report, AMEC achieved revenue of RMB 2.915 billion in the first quarter of 2026, a year-on-year increase of 34.13%; net profit reached RMB 930 million, a year-on-year increase of 197.20%. R&D investment during the same period was RMB 908 million, a year-on-year increase of 32.15%, accounting for 31.14% of revenue. The company stated that the performance growth was mainly due to increased shipments of etching equipment for advanced logic and memory chip processes, as well as the entry of some high-end products into mass production.

Yin Zhiyao also proposed at the time that the company planned to cover more than 60% of high-end key equipment for integrated circuits and more than 70% of advanced packaging equipment in about five years, and was committed to building a platform-based semiconductor equipment company.

Currently, AMEC is accelerating its capacity expansion. Its approximately 180,000-square-meter R&D and production base in Lingang, Shanghai, commenced operations in August 2024; the second phase of the Lingang base, covering approximately 200,000 square meters, is expected to begin construction in the second half of 2026. In addition, new bases in Chengdu and Guangzhou have also started construction. In the future, AMEC's total factory area in China will reach 850,000 square meters.

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[tokenanalyst]

Using Longitudinal Strong Focusing Principle to Lower Particle Beam Energy Spread Locally in a Storage Ring.​

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[tokenanalyst]

Data-driven elemental descriptors for rational design of high-sensitivity extreme ultraviolet photoresists.​

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Abstract​

The rational design of high-sensitivity photoresists for extreme ultraviolet (EUV) lithography is hindered by the lack of quantitative, predictive descriptors that link material composition to EUV absorption. Here, we develop a density-free, data-driven approach that quantifies both elemental sensitivity and impact. We introduce elemental sensitivity descriptors, μn and An, to estimate how elemental doping alters the linear attenuation coefficient and absorbance without requiring density information of the target material. Furthermore, we define elemental impact Δϕi to evaluate whether an element acts as a positive or negative contributor when embedded in high-absorption compounds. We identify I, Te, In, Sn, Sb, Cs, and Bi as top candidates for EUV photoresists, while revealing the detrimental role of H and C as matrix components. This work provides a generalizable strategy for EUV photoresist design.

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[tokenanalyst]

Oriental Crystal Technology Co., Ltd. has secured a major order from a leading domestic memory wafer foundry, ushering in a new era of computational lithography and AI etching.​

Orient Crystal Technology Co., Ltd. has signed a long-term strategic commercial contract worth nearly 200 million yuan with a leading domestic memory manufacturer. The partnership will leverage Orient Crystal's independently developed PanGen computational lithography platform and the world's first AI etching model, PanGen vPWQ, to accelerate the development of advanced memory process nodes.
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• PanGen Platform: A proprietary computational lithography solution that improves lithography accuracy and yield through precise algorithms and efficient computing.​
• PanGen vPWQ: The industry's first computational lithography tool to deeply integrate AI technology into etching modeling. It uses a hybrid approach combining traditional physical models with AI neural networks to predict post-etching pattern contours with high precision.​

Solves a critical industry challenge that traditional methods often stop defect prediction at the lithography stage and use simplified estimates for etching.

PanGen vPWQ accurately models the full etching process, capturing complex physical and chemical effects. It avoids AI overfitting By building AI on top of a physics-based framework, the system maintains reliability while adapting to production line variations.

Supports complex processes by handling multi-step patterning techniques like dual patterning (LELE) and self-aligned dual patterning (SADP), directly outputting final etching profiles. Auto Retargeting function by automatically optimizing existing OPC workflows to correct initial pattern targets, improving pattern fidelity on complex layouts while reducing manual engineering effort.

Benefits:​

• Higher yield: Accurate prediction of etching-related defects allows fabs to prepare contingency plans in advance.​
• Faster development: Reduces the number of tape-out iterations and shortens R&D cycles.​
• Lower costs: Decreases manual debugging time and minimizes mass-production risks.​
• Production-proven: Successfully validated on the customer's mass-production line, demonstrating measurable improvements in process development speed and yield.​

This cooperation represents more than a commercial deal. It marks a major milestone for domestically developed EDA tools in achieving breakthroughs in core advanced process technologies. Orient Crystal's HPO (Holistic Process Optimization) concept has moved from theory to real-world application, shifting from providing single tools to delivering intelligent, end-to-end yield improvement solutions that cover design, masks, lithography, and etching.

Orient Crystal will continue to deepen the integration of AI-driven modeling with electron beam metrology equipment by building a positive feedback loop where hardware enhances software and software optimizes hardware. The company is increasing R&D investment to address bottlenecks in advanced semiconductor processes and collaborate with industry partners to strengthen China's independent, secure, and efficient semiconductor ecosystem

As chip manufacturing approaches physical limits, yield management has become the key competitive factor. This partnership confirms that AI-enhanced computational lithography is essential for advancing process technology. Orient Crystal's innovations are helping China's semiconductor industry overcome critical challenges and move toward greater self-reliance.​

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[tamsen_ikard]

Huawei likes to show off but only when they can put their money where their mouth is. I suspect Hank is trying to do some confidence management against Huawei fans since there are a lot of folks in Chinese industry who don’t like Huawei’s aggressive tactics and eventually policymakers will have to curtail some of Huawei’s broader ambitions.

Why would the govt curtail huawei? Huawei is semi SOE. The more powerful huawei gets, the more powerful govt gets.

Huawei will never be curtailed

 

[tokenanalyst]

-Front End of the Line process optimizations, looks like they are going to continue developing new transistors architectures like GAA and Nanosheets, so geometrical scaling is still there but they are not going pursue aggressive geometrical scaling, using ALD and new materials they are going to reduce resistivity and capacitance in the interconnects of these transistors.

-Back End of the Line process optimizations, again ALD combined with new materials. Vertical integration means they are either going to develop 3D ICs by stacking layers vertically, my guest, using epitaxial deposition of doped Si or Ge to create a new layer for more transistors and connect them vertically and/or they are going to stack dies using hybrid bonders.

-Advanced packing optimizations, 3D integration of dies using hybrid bonders and ALD of low resistivity materials to fabricate the TSV interconnects.

-More Advanced packing optimizations.

 

[latenlazy]

3D Scaling with highly precise bonders

Eh what matters most here is the design approach.

 

[tokenanalyst]

Eh what matters most here is the design approach.

Of course.

 

[tokenanalyst]

Dinglong Technology's CMP polishing pad production capacity continues to rise, reaching 50,000 pieces per month.​

Dinglong Technology's production capacity for CMP polishing pads has significantly expanded to reach 50,000 pieces per month at its Wuhan headquarters, with the utilization rate rising steadily due to robust downstream demand. This growth aligns precisely with the expansion pace of major domestic wafer manufacturing and memory chip customers, ensuring that shipments match market needs while maintaining flexible delivery capabilities. The company reports deep customer coverage among key players, resulting in continuous order increases for polishing pads, which are supported by accelerating certifications for CMP slurries and growing market penetration across leading semiconductor foundries.

The company's financial performance reflects this operational momentum, with the first quarter of 2026 seeing operating revenue soar to RMB 1.02 billion (up 23.82% year-on-year) and net profit attributable to shareholders reaching RMB 251 million (a 77.99% increase). The CMP materials business is a primary driver of this success, while the display sector maintains stable order volumes and new businesses like high-end photoresists and advanced packaging materials are advancing through verification phases toward small-batch supply, positioning them as future growth engines alongside their established leadership in flexible display materials.

Strategically, Dinglong Technology continues to leverage its core technologies and localized service advantages to broaden certified product categories across the semiconductor value chain, from integrated circuit manufacturing to advanced packaging. Beyond semiconductors, the company is actively expanding into new energy lithium battery materials through its planned integration of Haofei New Materials, focusing on organizational optimization and quality control to empower technology iteration. As a leading domestic platform for innovative materials, Dinglong aims to solidify its position as a critical supplier across multiple high-growth industry sectors while navigating ongoing investments in emerging material technologies.​

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[ZeEa5KPul]

https://twitter.com/i/web/status/2058807182649328045

this is rather an interesting point. If we do use 171MTr/mm2 (which is not the calculation that TSMC uses) for N5, then looks like the HW's folding design needs a process that is close to N5 to achieve so much higher transistor density.

Just to elaborate on this, N5 was the first TSMC node to use EUV.