Chinese semiconductor thread II

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A Sige Channel Gate-All-Around Transistor Fabricated Using Novel Cyclic Self-Limiting Wet Etching Combined with SI Removal Process.​


Institute of Microelectronics
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Abstract:​

In this work, a novel SiGe channel gate-all-around (GAA) transistor using a cyclic self-limiting wet etching process combined with Si removal process after dummy gate removal in the mainstream FinFET process is demonstrated in detail. The width of SiGe channel is narrowed from 20 nm to 6.5 nm and its mole fraction of Ge of SiGe channel can be increased from 31.8% to ~40%. Meanwhile, IDS of 382 μA/μm is obtained at VDS = VGS = -0.8V, with ION/IOFF ratio of ~5.5e5 and SS of 76 mV/dec. These results prove that this novel process provides a potential solution to prepare the SiGe channel GAA transistor.​

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A Novel Load-Si-Cut SOI Nanosheets Transistors with Ultrathin SiGe Cladded Si Channel Structure to Suppress Leakage and Enhance Driven Current.​

Institute of Microelectronics​

Abstract:​

In this article, we propose a novel load-Si-cut silicon-on-insulator (SOI) nanosheets transistors (NSFETs) with ultrathin SiGe cladded Si channel structure, named as LSC-SOI NSFETs, improving the drive current and suppressing leakage issues in the conventional SOI (C-SOI) NSFETs. The electrical characteristics of PMOS device, inverters and ring oscillators (RO) of C-SOI and LSC-SOI NSFETs were investigated using 3D technology computer-aided design (TCAD) simulation.​

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Performance Improvement of Monolithic CFET by Backside Enhanced Contact with C-type Source/Drain Contact Technology​

Institute of Microelectronics
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Abstract:​

In this paper, to optimized source/drain (S/D) contact in monolithic CFET, the backside enhanced contact (BSEC) technology is proposed and investigated by TCAD simulation, which can be used to form C-type S/D contact. Compared with the conventional L-type contact of common drain in monolithic CFET, the on-current (Ion) of bottom PFET with C-type S/D contact shows a 25.4% increase as the contact resistivity is 3e-9 Ω•cm2, and the Ion of top NFET has little affects. Furthermore, the C-type S/D contact based on BSEC technology is conducive to further improving bottom PFET’s driving performance, relieving the Ion mismatch between PFET and NFET for monolithic CFET, and optimizing the transient characteristics of CFET inverter.​

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High-Resolution Patterning of Directed Self-Assembly (DSA) Lithography Via Universal Orientation Control Method​

Abstract:​

Directed self-assembly (DSA), as an emerging nano-manufacturing technology, demonstrates significant potential in advanced nodes in semiconductor field. This paper reports a method for controlling the domain orientation of fluorinated block copolymers (named as FV-1) on graphoepitaxy template, successfully producing high-resolution line and contact hole patterns with dimensions as small as 8 nm, without using molecular brushes or topcoat materials. This method realizes the combination with traditional lithography techniques, overcoming the limitations of lithography when scaling down. And the process flow is relatively simple, highlighting its strong application prospects.​

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Naura is working hard in increasing the productivity of multi-patterning techniques with immersion lithography.

The Influence of Mandrel Materials in Self-Aligned Multiple Patterning Process​


Beijing NAURA Microelectronics Equipment Co. Ltd

Abstract:​

Due to limitations in lithography resources, the application of immersion lithography in advanced nodes has reached a bottleneck. The Self-Aligned Double Patterning (SADP) and Self-Aligned Quadruple Patterning (SAQP) processes within Double Patterning Technology (DPT) not only ensure precise overlay accuracy but also effectively reduce pitch, making them essential in the production of high-end process chips. However, different devices have varying material requirements and technical standards for SADP or SAQP. Thus, the impact of the SADP film layer structure design—particularly material selection—on the final process outcomes has received increasing attention. This paper compares the effects of poly and carbon mandrels on SADP pattern transfer, focusing on mandrel material formation, key step profiles, and line roughness. It also discusses how process optimization and material selection can further enhance SADP performance.​

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Shengmei: Orders for the fourth quarter are about to be fully booked​



Shengmei Shanghai recently revealed that the company's current order situation is good, with orders for the third quarter already fully booked and the fourth quarter about to be fully booked, showing the company's strong business development momentum.
Shengmei Shanghai recently revealed that the company's current order situation is good, with orders for the third quarter already fully booked and the fourth quarter about to be fully booked.

According to the latest research information from Shengmei Shanghai, it is expected that furnace tube series equipment including LPCVD, oxidation furnace and ALD will achieve significant volume growth in 2025. In addition, electroplating equipment is growing rapidly, basically maintaining a 50% growth this year, and is expected to maintain a rapid growth trend next year.

ACM Shanghai is an important company in the field of domestic semiconductor equipment, with a current market value of 46.8 billion yuan and a price-earnings ratio of 47.54. Against the backdrop of adjustments in the semiconductor industry as a whole, ACM Shanghai's full order book shows the company's competitive advantage and market recognition in the sub-sector.

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