Chinese semiconductor thread II

[tphuang]

I looked into it. H100’s peak power consumption is 700 watts. Ascend 910’s is 310 watts.

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sure, but Ascend-910C is likely going to require more power also. And we don't know what that will be. After all, A100 consumes 250-300w, depending on which source you use.

I'm not saying Ascend-910C won't have lower power consumption. Just that we don't know.

Energy efficiency is still a concern. The energy in China isn’t that cheap where we can just hand wave concerns away.

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More than half the cost from data centers in China come from power consumption and approximately 25% is coming from depreciation.

Pretty small concern. The fruit of computation will be far more than that. There are more reasons than that to worry about with energy efficiency

 

[tphuang]

https://twitter.com/i/web/status/1823787126598615134

BYD Semi makes all sort of CMOS imaging sensors, including 3 and 8.3MP for ADAS. This is how it keeps cost down.

 

[latenlazy]

Do you know what energy efficiency is? It's not the maximum power consumption. It's how much compute you can get per watt. It is extremely unlikely HUAWEI will match Nvidia on energy efficiency. They are still 2-3 node shrinks behind Nvidia. It is extremely difficult for any architectural change to compensate for being behind in node shrinks and even if it did it almost always comes at a cost at performance somewhere else.
.

1 tflop/310 W vs 1.4 flop/700 W. Do you not know how to math?

If you knew how poorly optimized GPUs are for NN applications you wouldn't be so fixed on node shrinks.

sure, but Ascend-910C is likely going to require more power also. And we don't know what that will be. After all, A100 consumes 250-300w, depending on which source you use.

I'm not saying Ascend-910C won't have lower power consumption. Just that we don't know.

I mean, I think it's extremely unlikely that 910C will have worse power efficiency scaling than 910 since it's an iteration, but okay.

 

[taxiya]

What is the impact of Chinese semiconductor chip production?

bloomberg

US Floats Tougher Trade Curbs in Chip Crackdown on China​

• Restrictions would hit technology from Tokyo Electron and ASML

ASML said in a statement that second-quarter net sales were 6.24 billion euros, exceeding market expectations of 6 billion euros. Bookings increased 54% to 5.57 billion euros ($6.1 billion), exceeding the consensus of 4.41 billion euros.
China accounted for almost half of ASML's second quarter sales, up €390 million from the previous quarter.

Who cares? US has been throwing so many boots on the floor that China does not bother anymore.

 

[curiouscat]

1 tflop/310 W vs 1.4 flop/700 W. Do you not know how to math?

If you knew how poorly optimized GPUs are for NN applications you wouldn't be so fixed on node shrinks.



I mean, I think it's extremely unlikely that 910C will have worse power efficiency scaling than 910 since it's an iteration, but okay.

It’s 1 tflop per watt for HUAWEI vs 1.4 tflop per watt for Nvidia. I think you need to brush up on how fractions work.

 

[latenlazy]

It's 1 tflop per watt for HUAWEI vs 1.4 tflop per watt for Nvidia. I think you need to brush up on how fractions work.

No, just misread pecopls’s comment.

 

[tokenanalyst]

Ultrathin Small Outline Package Key Techniques for High-Speed Chips with Multi-Leads.​

School of Electronic and Information Engineering, Lanzhou Jiaotong University.
School of Electronic Information and Electrical Engineering, Tianshui Normal University.
Engineering Research Center, Ministry of Education on Integrated Circuit Packaging and Testing.
Tianshui Huatian Science and Technology Co., Ltd.
​

Abstract​

The key technologies for the ultrathin small outline package (TSOP) of large-sized high-speed chips have been designed and developed in this paper. The designing techniques, such as a 25 µm precise positioning dice attaching technique, a lead frame unit structure without a base island, and a lead co-plane layout inside the frame, were developed. The TSO package outline with a large number of leads, a frame unit arrangement, and a frame distribution with a base island and without one were improved. The technological problems, including the reduction in thickness, wafer cutting, chip sticking bonding, and plastic sealing, were successfully solved. The designed large-sized package products have many advantages, such as high availability, low cost, high reliability, and a short production cycle. This package technique can be widely used in various intellectual application regions.​

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[pecopls]

Another thing that's underrated is system-level power efficiency (i.e., including power for CPU, networking, etc.). After all, data center power draw is more than just the cards, you also need to consider the entire system and the data center efficiency (PUE) itself.

We can calculate the

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. Not pictured is the H100 SuperPOD, but the answer to that is

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.

A proper calculation also factors in PUE, which is how many excess watts the data center draws to generate one watt. For instance, a PUE of 1.1 is excellent, which means that for every 1 watt used to generate compute, 1.1 watts are pulled from the grid. H100 and A100 systems generally have a PUE of 1.25, while Atlas 900/Ascend 910 is rated at the much better 1.15.

Finally, I'll point out that energy efficiency gains aren't purely tied to node scaling. NVIDIA's B200 and H100 are both using TSMC 4N, and yet the energy efficiency of the B200 is ~65% better than the H100. At a card level (i.e., not system level as calculated above) B200 generates 2.3 FP16 TFLOPS/W vs. H100's 1.4 FP16 TFLOPS/W. So we can't write off further efficiency improvements for Huawei's next accelerator either, even if they stick with SMIC's N+2.

 

[curiouscat]

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I’ve personally met Alex Padilla before when I was in D.C. This letter from him and Zoe Lofgren carry substantial weight IMO. I think they’re getting pretty concerned the sanctions on China are backfiring.

 

[latenlazy]

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I’ve personally met Alex Padilla before when I was in D.C. This letter from him and Zoe Lofgren carry substantial weight IMO. I think they’re getting pretty concerned the sanctions on China are backfiring.

They don’t have any real weight in DC in foreign policy matters. Even the whole Silicon Valley tech lobby has very limited influence relative to the Natsec and defense lobbies in that domain. They’re not swinging the rest of Congress with them and the only potential way their views will have an impact is if they get some inside track influence on cabinet appointments or a direct line to the President’s ear.