Chinese semiconductor thread II

[tokenanalyst]

Gaoshi Semiconductor's nano-scale pattern wafer defect detection mass production equipment is exported to Malaysia's leading customer.​

At the beginning of the new year in 2024, Suzhou Gaoshi Semiconductor's nano-scale pattern wafer defect detection mass production equipment, 2D & 3D inspection, will be exported to Malaysia's top customers. Gaoshi Semiconductor has been committed to the development and manufacturing of semiconductor wafer inspection equipment, and has been recognized by many domestic and foreign customers over the years.



Gaoshi Semiconductor has been adhering to the localization of semiconductor equipment and promoting the development of the domestic visual field. By constantly cultivating internal skills and overcoming technical difficulties, we have delivered batches of equipment to customers in China. At the same time, we aim at the international market, break through the country, and demonstrate domestic visual inspection technology on the international stage.

Gaoshi Technology (Suzhou) Co., Ltd. was established in 2015. It is an overall solution provider for industrial vision based on AI. The company has three major business segments: semiconductor industry inspection, screen industry inspection, and new energy industry inspection. It has an industry-experienced professional R&D team, with R&D personnel accounting for more than 80%, and the average annual scientific research investment accounting for more than 20%. In recent years, the semiconductor industry represented by wafer chips has become a national strategic emerging industry. Its subsidiary Suzhou Gaoshi Semiconductor Technology Co., Ltd. is a high-tech modern company with machine vision and artificial intelligence as its technical core, focusing on the optical inspection link in the front-end and back-end semiconductor wafer manufacturing processes, and providing inspection equipment and solutions to the industry. . The products cover all aspects and technology nodes of the semiconductor wafer process, including patternless wafer inspection, patterned wafer inspection and measurement, 2D & 3D critical dimension measurement, accurate defect classification (ADC) and process and quality management system (GOINFO) , providing data analysis and process guidance for semiconductor wafer manufacturing processes.

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[tokenanalyst]

Interesting conferences From SPIE 2024

Etching


Aquiliary equipment

 

[tokenanalyst]

Novel patterning techniques



Metrology

 

[tokenanalyst]

Litho



EUV

 

[tokenanalyst]

Two new GaN projects signed in Fuzhou New District​

Recently, Fuzhou New District has signed 38 key projects with a total investment of more than 22 billion yuan, two of which involve gallium nitride, including the Core Semiconductor gallium nitride wafer fab project and the Fuzhou Gallium Valley gallium nitride epitaxial wafer project.

Information shows that the Xinrui Semiconductor gallium nitride wafer fab project is constructed by Fujian Xinrui Semiconductor Co., Ltd. Xinrui Semiconductor was established in December 2023 with a registered capital of 5 billion yuan.

The Fuzhou Gallium Valley gallium nitride epitaxial wafer project is constructed by Fuzhou Gallium Valley Semiconductor Co., Ltd. It is mainly engaged in the research and development and production of third-generation semiconductors. It is expected to invest 1 billion yuan and cover 86 acres of land. After reaching production, the annual production capacity will be 240,000 wafers.

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[tokenanalyst]

Qingyi Optoelectronics plans to build a high-end semiconductor mask production base in Nanhai, Foshan​

On January 29, Foshan Qingyi Microelectronics Co., Ltd. won the bid for No. 6 Danfeng Road, Danzao Town, Nanhai District, Foshan City, with an area of 19,167.02 square meters (approximately 28.75 acres). It plans to build a high-end semiconductor mask. Membrane production base. The total planned investment is 1.5 billion yuan (of which about 800 million yuan is fixed investment).

It is understood that Foshan Qingyi Microelectronics Co., Ltd. is a wholly-owned subsidiary of Shenzhen Qingyi Optoelectronics Co., Ltd. (hereinafter referred to as "Qingyi Optoelectronics"). Qingyi Optoelectronics was founded in 1997 and went public in 2019. It is mainly engaged in the research and development, design, production and sales of masks. It is one of the earliest and largest leading mask production companies in China. The company's products are mainly used in flat panel displays, semiconductor chips, touch, circuit boards and other industries.

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[tokenanalyst]

Chris Miller pretending he didn’t write what he wrote 3 years ago.

Chris Miller on China's legacy chips expansion. Some interesting comments:

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When an Engineer wake up to the Think Tank "experts" nightmarish reality that is plaguing the policy decisions in D.C. and the semiconductor industry.

 

[latenlazy]

When an Engineer wake up to the Think Tank "experts" nightmarish reality that is plaguing the policy decisions in D.C. and the semiconductor industry.

View attachment 124622View attachment 124624

When you talk about technology like it’s fantasy magic.

 

[tphuang]

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very good article here from CETC on Silicon Carbide

中国电科自主研制的40台碳化硅外延炉成功进驻客户现场

40 SiC epitaxial furnaces by CETC were introduced at customer site

团队自研碳化硅单晶生长炉，完成高纯碳化硅粉料制备，突破4英寸、6英寸碳化硅衬底产业化关键技术，攻克N型碳化硅单晶衬底、高纯半绝缘碳化硅单晶衬底制备难题，解决“切、磨、抛”等工艺难点，实现碳化硅粉料制备、单晶生长、晶片加工等全流程自主创新。2023年，团队成功实现8英寸碳化硅单晶及衬底小批量出货，6英寸中高压碳化硅外延片月产能力大幅提升。

CETC does R&D for furnaces, preparation of SiC powder, industrialization of 4/6-inch SiC substract, N-type Sic Single Crystal substrate & high purity semi-insulating SiC substrate, how to cut/grind/polish the wafer.
they achieved small batch shipment of 8-inch SiC substrate and increased production of 6-inch medium/high-V Sic epitaxial wafers

8-inch produces 90% more chips & lower unit cost by 50% per chip vs 6-inch

“这是一个1200伏、100安的碳化硅半导体器件，电能的处理和控制，靠的就是这个。”小心翼翼用真空吸笔拾取碳化硅器件，技术专家笑着说，随着国产新能源汽车生产量迅猛攀升，碳化硅材料研制的器件、模块，快速走向应用舞台“C位”。相同规格下碳化硅MOSFET的尺寸只有硅基产品的1/10，但导通电阻是后者的百分之一，总能量损耗可以降低70%。

each SiC MOSFET is only 1/10 that of Si based products, resistance is 1% of Sic & total energy loss reduced by 70%
This is for 1200V, 100A SiC device

基于碳化硅的新一代新能源汽车平台，可使充电速度提高5-10倍，续航里程提高8%以上，损耗降低50%。中国电科持续推进新能源汽车用碳化硅MOSFET关键核心技术攻关和产业化应用，贯通碳化硅衬底、外延、芯片等全产业链量产平台，在新能源汽车、光伏、智能电网等领域规模化应用，研制的新能源汽车用650V-1200V碳化硅MOSFET出货量突破1500万只，累计保障超过200万辆新能源汽车应用需求。

NEV platform using SiC increase charge speed by 5-10x, range go up 8% & loss drops 50%

CETC achieving sales of 15 million 650-1200V SiC MOSFET unit for NEVs, enough for 2 million cars

 

[tokenanalyst]

The Institute of Microelectronics of the Chinese Academy of Sciences has made important progress in the research field of 3D DRAM with CAA structure.​

DRAM is one of the most important branches in the memory field. As the size shrinks, the storage capacitance limitation of 1T1C structure DRAM becomes more and more obvious, causing traditional 1T1C-DRAM to face scaling challenges. 2T0C-DRAM based on indium gallium zinc oxide (IGZO) transistors is expected to overcome the scaling challenges of 1T1C-DRAM and exert greater advantages in 3D DRAM. However, current research work is based on planar structure IGZO devices, and the resulting 2T0C unit size (approximately 20F 2 ) is much larger than the 1T1C unit size (6F 2 ) with the same feature size , making IGZO-DRAM lack the density advantage.



In response to the density issue of planar structure IGZO-DRAM, the team of Academician Liu Ming of the Key Laboratory of Microelectronics, Chinese Academy of Sciences reported the basis of the vertical annular channel structure (Channel-All-Around, CAA) IGZO transistor at the 2021 and 2022 IEDM International Conferences. On the above, the ALD process of depositing IGZO channels was analyzed to regulate device performance and stability, and the impact of stacking the second layer of IGZO transistors on the performance of the first layer of devices was studied. On this basis, a 4F 2 2T0C DARM unit based on vertically stacked CAA IGZO transistors was successfully realized for the first time . The upper and lower layers of transistors showed good device performance and stability. The resulting 2T0C DRAM unit achieved a retention time of 75 seconds and showed no performance degradation after 10 +11 write and erase operations.

This research result proves the feasibility of stacked CAA IGZO 2T0C structure and helps promote the application of IGZO DRAM in three-dimensional high-density DRAM. The article "First Demonstration of Stacked 2T0C-DRAM Bit-Cell Constructed by Two-Layers of Vertical Channel-All-Around IGZO FETs Realizing 4F 2 Area Cost" based on this achievement was selected for the 2023 IEDM. Chen Chuanke, a doctoral student at the Institute of Microelectronics, Chinese Academy of Sciences, is the first author, and associate researcher Xiang Jinjuan from the Beijing Institute of Superstring Memory is the co-first author. Researchers Li Ling and Geng Wei from the Institute of Microelectronics, Chinese Academy of Sciences, and researcher Zhao Chao from the Beijing Institute of Superstring Memory.

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