Nucleisys releases the 1000 series cores, opening a new chapter of out-of-order high performance
2024-03-18
Nucleisys, a local leader in RISC-V CPU IP, officially released the UX1000 series, a high-performance commercial processor CPU IP based on the RISC-V instruction set, providing domestically produced RISC-V CPU IP for high-performance processor cores.
...
The newly released UX1000 series by Nucleisys is a 64-bit high-performance application processor with multiple decoding widths, out-of-order launch and execution capabilities. It is mainly targeted at network processing, artificial intelligence, autonomous driving, data center accelerator cards, and high-performance applications such as mobile devices which further meet the growing local demand for domestically produced high-performance processor IP.
The UX1000 series has a highly configurable pipeline that users can customize based on different performance requirements, providing strong flexibility in system design:
The UX1000 series is available in three different configuration categories: UX1030, UX1040 and UX1060
UX1030: 3 decoding width processor
- Has better performance and lower area power consumption
UX1040: 4 decoding width processor
- Has high performance and excellent area and power consumption
UX1060: 6 decoding width processor
- Has higher performance, mainly for high-performance applications
...
Single core features
The UX1000 series processor is a 12-stage pipeline out-of-order execution processor based on RISC-V RV64IMAFDCVBKZfh and strictly follows RISC-V standard instructions;
UX1000 has strong computing power and supports issue width (Issue Width) of up to 10 scalar instructions and 2 vector instructions per cycle;
Configurable instruction and data cache (ICache / DCache) and on-chip SRAM (ILM / DLM) and supports ECC;
In terms of memory access design, UX1000 supports private L2 cache, providing more efficient data reading and storage capabilities;
Supports the VPU vector computing unit that strictly follows the RISC-V Vector 1.0 standard. It has 2 computing pipeline units and 1 data reading and writing pipeline. It can be configured with 128b/256b VLEN and supports INT8/16/32/64 and BF16/F16. /F32/F64 data type.
Multi-core configurable features
Supports up to one Cluster 8 cores and cache consistency;
Configurable private L2 and Cluster Cache;
Configurable IO consistency interface (IOCP). With the help of IOCP interface, external devices (such as NPU, accelerator, PCIe, DMA, etc.) can share data reading with Core and Cluster cache and maintain cache consistency;
Cluster Cache supports SECDED ECC;
Supports configuring Cluster Cache as Cluster Local Memory and can support CLM interface.
...