Chinese semiconductor thread II

tokenanalyst

Lieutenant General
Registered Member

An Effective Hybrid Rescheduling Method for Wafer Chip Precision Packaging Workshops in Complex Manufacturing Environments.​

Abstract​

With the continuous development of semiconductor manufacturing technology and information technology, the sizes of wafer chips are becoming smaller and the variety is increasing, which has put forward high requirements for wafer chip precision manufacturing and packaging workshops. On the one hand, the market demand for multiple varieties and small batches will increase the difficulty of scheduling. On the other hand, the complex manufacturing environment brings various types of dynamic events that will disrupt production plans. Accordingly, this work researches the wafer chip precision packaging workshop rescheduling problem under events of machine breakdown, emergency order inserting and original order modification. Firstly, the mathematical model for the addressed problem is established, and the rolling horizon technology is adopted to deal with multiple dynamic events. Then, a hybrid algorithm combining an improved firefly optimization framework and variable neighborhood search strategy is proposed. The population evolution mechanism is designed based on the location-updating law of fireflies in nature. The variable neighborhood search is applied for avoiding local optima and sufficiently exploring in the neighborhood. At last, the test results of comparative experiments and engineering cases indicate that the proposed method is effective and stable and is superior to the current advanced algorithms.

1765638670120.png

Please, Log in or Register to view URLs content!
 

tphuang

General
Staff member
Super Moderator
VIP Professional
Registered Member
This guy is a questionable source. He claims to be an employee from TSMC but I highly doubt a TSMC employee would post random Weibos like this.

The number he provided based on TechInsight calculation makes sense. N+2 matches what hvpc showed to me back in early 2024. N+3 being a 20-25% improvement in transistor density seems reasonable. They got a 10% shrink on both side.

He seems to be giving a different transistor density based on his own calculation also. Which is whatever, who cares. Using his number, N+3 is basically half way between N7 and N5.
 
Top