Chinese semiconductor thread II

[tphuang]

Silergy showcased its digital EDA solutions at the 2025 China International Import Expo, empowering industrial innovation.​

At the 2025 China International Import Expo, Sirchip's booth in the Lingang exhibition area received numerous visitors. As a representative company in the digital EDA field, Sirchip showcased a series of cutting-edge technologies and innovative achievements in chip design verification, attracting many professional visitors from home and abroad to stop and exchange ideas.

01 Highlights of the CIIE

Silergy showcased tools for architecture design, software simulation, hardware simulation, prototype verification, and verification cloud services, demonstrating its comprehensive service capabilities for digital circuit design and implementation in fields such as artificial intelligence, high-performance computing, and image processing. Of particular note was Silergy's "ChipEye" prototype verification solution, embodying over two decades of technological accumulation. Its superior performance and continuous innovation made it an unsurprisingly popular exhibit in the area. A senior engineer from Japan stated at the event that Silergy's outstanding product capabilities and professional services are the fundamental reasons for their continued choice of the company.
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02 Addressing Global Chip Verification Challenges

With the rapid development of AI technology, the global integrated circuit design industry is facing unprecedented challenges. At the China International Import Expo (CIIE), a technology expert from Silergy pointed out: "The rapid development of AI applications has ushered in an era of hundreds of billions of gates in chip design, with software code volume surging to the hundreds of millions of lines, making design verification increasingly difficult." To address these challenges, Silergy has proposed three major development paths: a left-shift development strategy to provide overall solutions, in-depth cooperation with mainstream architecture and IP vendors to build an ecosystem, and the development of application-level innovative solutions adapted to emerging applications such as automotive and IoT.
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The company has already established strong partnerships with over 600 enterprises worldwide, and its products are widely used in terminal fields such as the Internet of Things, cloud computing, 5G communications, smart healthcare, and automotive electronics. Through the China International Import Expo (CIIE), Silergy has further expanded its international influence.

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I don't think this is Silergy. Silergy website is here

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this is 思尔芯

 

[tokenanalyst]

I don't think this is Silergy. Silergy website is here

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this is 思尔芯

The news is from their own website. Could be a mistranslation.
Their name is S2C EDA, the Silergy could come from the "S"

 

[tonyget]

DRAM – Q3 2025 Update​

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1. Executive Summary​

In this third issue of the 2025 DRAM quarterly update, TechInsights provides an update on the ongoing DRAM analysis. This issue also looks at the recent Winbond, Nanya, and CXMT devices and recaps the 10 nm class DRAM nodes.

2. Recent devices from Winbond, Nanya, and CXMT​

Table 2.0.1 shows the recent Winbond [1], Nanya [2], and CXMT [3] devices. All three devices adopt the 7.8F2 DRAM cell layout, with active inclined at 69 degrees to the word line (WL). The DRAM feature size (F) is calculated from the unit cell area, which is the product of the WL pitch and bit line (BL) pitch (valid for the 7.8F2 DRAM cell layout). The active half-pitch (HP) is generally a few nanometers smaller than the DRAM feature size (F).

Ref.	Foundry	Label	Active Pitch (nm)	WL Pitch (nm)	BL Pitch (nm)	Cell 7.8F2 (µm2)	Feature F (nm)
[ Please, Log in or Register to view URLs content! ]	Winbond	20 nm	40	56	64	0.00358	21.44
[ Please, Log in or Register to view URLs content! ]	Nanya	1B	33.5	45.8	53.6	0.00245	17.74
[ Please, Log in or Register to view URLs content! ]	CXMT	G4	29.5	41.7	47.9	0.002	16

Table 2.0.1: Comparison of most advanced devices from Winbond, Nanya, and CXMT. TechInsights, 2025.​

Winbond 20 nm DRAM falls under D2z (third generation of the 20 nm class DRAM node), Nanya 1B DRAM is comparable to D1y (second generation of the 10 nm class DRAM node), and CMXT G4 DRAM is on par with D1z (third generation of the 10 nm class DRAM node).

DRAM	Active HP (nm)				Cell 7.8F2 (µm2)				Feature F (nm)
Node	Samsung	SK hynix	Micron	CXMT	Samsung	SK hynix	Micron	CXMT	Samsung	SK hynix	Micron	CXMT
D1x	17	17	19	17	0.00253	0.00253	0.00328	0.00253	18.0	18.0	20.5	16.0
D1y	16	16	17	-	0.00225	0.00218	0.00239	-	17.0	16.7	17.5	-
D1z	15	15	15	15	0.00192	0.00200	0.00200	0.00200	15.7	16.0	16.0	15.0
D1a	13	14	14	-	0.00151	0.00176	0.00166	0.00176	13.9	15.0	14.6	-
D1b	12	12	12	-	0.00124	0.00126	0.00132	-	12.6	12.7	13.0	-
D1c	-	-	-	-	0.00100	0.00101	0.00107	-	11.3	11.4	11.7	-
D1d	-	-	-	-	0.00081	0.00083	0.00086	-	10.2	10.3	10.5	-
D1d*	-	-	-	-	0.00086	0.00088	0.00091	-	10.5	10.6	10.8	-
D1e*	-	-	-	-	0.00078	0.00080	0.00080	-	10.0	10.1	10.3	-

*: less aggressive scaling at D1d node leads to addition of D1e node

Table 2.0.2: 10 nm class DRAM nodes of Samsung, SK hynix, Micron, and CXMT. TechInsights, 2025.​

TechInsights had analyzed five generations of 10 nm class DRAM nodes (D1x, D1y, D1z, D1a, D1b) from the three major vendors (Samsung, SK hynix, and Micron). The sixth generation (D1c), with a 10 % shrink, is around the DRAM feature size of 11 nm. The seventh generation (D1d) may continue as 10 % shrink or at a less aggressive scaling of 7 to 8 % shrink, allowing another generation (D1e) before conversion to 4F2 or 3D DRAM. Micron might be the only one to adopt D1e. CXMT had G1 (D2y), G3 (D1x), and G4 (D1z) available, and is likely to continue to skip some nodes to shorten the gap between itself and the other major vendors.

 

[tphuang]

DRAM – Q3 2025 Update​

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1. Executive Summary​

In this third issue of the 2025 DRAM quarterly update, TechInsights provides an update on the ongoing DRAM analysis. This issue also looks at the recent Winbond, Nanya, and CXMT devices and recaps the 10 nm class DRAM nodes.

2. Recent devices from Winbond, Nanya, and CXMT​

Table 2.0.1 shows the recent Winbond [1], Nanya [2], and CXMT [3] devices. All three devices adopt the 7.8F2 DRAM cell layout, with active inclined at 69 degrees to the word line (WL). The DRAM feature size (F) is calculated from the unit cell area, which is the product of the WL pitch and bit line (BL) pitch (valid for the 7.8F2 DRAM cell layout). The active half-pitch (HP) is generally a few nanometers smaller than the DRAM feature size (F).

Ref.	Foundry	Label	Active Pitch (nm)	WL Pitch (nm)	BL Pitch (nm)	Cell 7.8F2 (µm2)	Feature F (nm)
[ Please, Log in or Register to view URLs content! ]	Winbond	20 nm	40	56	64	0.00358	21.44
[ Please, Log in or Register to view URLs content! ]	Nanya	1B	33.5	45.8	53.6	0.00245	17.74
[ Please, Log in or Register to view URLs content! ]	CXMT	G4	29.5	41.7	47.9	0.002	16

Table 2.0.1: Comparison of most advanced devices from Winbond, Nanya, and CXMT. TechInsights, 2025.​

Winbond 20 nm DRAM falls under D2z (third generation of the 20 nm class DRAM node), Nanya 1B DRAM is comparable to D1y (second generation of the 10 nm class DRAM node), and CMXT G4 DRAM is on par with D1z (third generation of the 10 nm class DRAM node).

DRAM	Active HP (nm)				Cell 7.8F2 (µm2)				Feature F (nm)
Node	Samsung	SK hynix	Micron	CXMT	Samsung	SK hynix	Micron	CXMT	Samsung	SK hynix	Micron	CXMT
D1x	17	17	19	17	0.00253	0.00253	0.00328	0.00253	18.0	18.0	20.5	16.0
D1y	16	16	17	-	0.00225	0.00218	0.00239	-	17.0	16.7	17.5	-
D1z	15	15	15	15	0.00192	0.00200	0.00200	0.00200	15.7	16.0	16.0	15.0
D1a	13	14	14	-	0.00151	0.00176	0.00166	0.00176	13.9	15.0	14.6	-
D1b	12	12	12	-	0.00124	0.00126	0.00132	-	12.6	12.7	13.0	-
D1c	-	-	-	-	0.00100	0.00101	0.00107	-	11.3	11.4	11.7	-
D1d	-	-	-	-	0.00081	0.00083	0.00086	-	10.2	10.3	10.5	-
D1d*	-	-	-	-	0.00086	0.00088	0.00091	-	10.5	10.6	10.8	-
D1e*	-	-	-	-	0.00078	0.00080	0.00080	-	10.0	10.1	10.3	-

*: less aggressive scaling at D1d node leads to addition of D1e node

Table 2.0.2: 10 nm class DRAM nodes of Samsung, SK hynix, Micron, and CXMT. TechInsights, 2025.​

TechInsights had analyzed five generations of 10 nm class DRAM nodes (D1x, D1y, D1z, D1a, D1b) from the three major vendors (Samsung, SK hynix, and Micron). The sixth generation (D1c), with a 10 % shrink, is around the DRAM feature size of 11 nm. The seventh generation (D1d) may continue as 10 % shrink or at a less aggressive scaling of 7 to 8 % shrink, allowing another generation (D1e) before conversion to 4F2 or 3D DRAM. Micron might be the only one to adopt D1e. CXMT had G1 (D2y), G3 (D1x), and G4 (D1z) available, and is likely to continue to skip some nodes to shorten the gap between itself and the other major vendors.

are you sure that 15.0 Feature F for CXMT in D1z is correct? The first table had it as 16 (and I believe that's the correct value).

Also, how did it get a 0.00176 µm2 Cell for CXMT if it hasn't examine a D1a product yet?