With miniaturization at a wall, upstarts gain edge in race for faster chips
KEN KOYANAGI, Nikkei Asia Editor-at-largeOctober 21, 2020 17:54 JST
TOKYO -- Yukio Sakamoto, a 73-year-old Japanese chipmaking business veteran, last fall took a senior vice president position at Tsinghua Unigroup, a leading Chinese high-tech conglomerate affiliated with the renowned Tsinghua University. His role is to oversee the launching of a DRAM memory-chip manufacturing business.
It looked like a bold decision and perhaps an ill-conceived move considering the U.S.-China technology rivalry was growing nastier. The U.S. continues to throw one punch after another at Chinese semiconductor makers Huawei Technology and Semiconductor Manufacturing International Corp., known as SMIC, making the idea of launching a new chipmaking business in China appear daunting.
But Sakamoto remains optimistic.
"We are living in a world where latecomers have a better chance to catch up with incumbent leaders," he told Nikkei Asia, "because semiconductor technology is progressing more slowly today as the smallness of transistors is approaching limits in terms of physics and optics."
He is not talking about the near-term conditions for building a new memory-chip factory, which are far from ideal. It is uncertain how long Chinese companies will be allowed to import U.S. chipmaking equipment and chip-designing software, though as of Oct. 19 Unigroup has not been named as a restriction target by any U.S. government agency.
Rather, Sakamoto is talking about the longer-term prospects for China to develop its own silicon wafer fabrication skills and technological capabilities for domestically supplying chipmaking materials, equipment and software.
History tells us that a technology paradigm shift can create opportunities for emerging players, and Sakamoto is seeing this unfold in the semiconductor sector today.
Rise of 3D tech
Moore's Law remains on the books. It says that the number of transistors in an integrated-circuit chip doubles every 18 to 24 months. It was foretold by Intel co-founder Gordon Moore in the 1960s. Until the mid-2000s, the industry kept pace with the law by shrinking the size of transistors and circuits built on a surface of a silicon wafer die.
But miniaturization hit a wall about 15 years ago. The size of transistors had shrunk to about 30 nanometers (30 billionths of a meter), measured by the width of a central electrode called a "gate." Therefore the speed of miniaturization slowed.
Chipmakers have nonetheless kept reducing the numbers labeling their latest generations of chips, going from 32nm to 22nm, to 14nm and to 10nm. But these numbers stopped representing actual transistor-gate sizes after the mid-2000s, becoming something like brand labels.
For example, the actual gate length of a transistor in a "7nm" logic chip made last year by Taiwan Semiconductor Manufacturing Corp., known as TSMC, was somewhere around 18 nm, according to University of Tokyo professor Toshiro Hiramoto. It is a stark deviation from the "32 nm" chips, whose gate length was actually 32 nm or smaller.
Because of the increased difficulty and rising cost of miniaturization, chipmakers are turning to so-called three-dimension technologies that make use of the space above the conventional wafer surface to load more transistors onto a chip.
For example, the most advanced NAND flash memory chip, commonly used for data and image storage in smartphones and personal computers, is structured in as many as 96 to 128 layers of integrated circuits stacked on top of the bottom wafer die.
While the layers increase and the whole chip thickens, transistor miniaturization has reversed itself in the world of flash memory.
Today, the typical transistor size of a flash chip is somewhere in the 22-32 nm range, larger than the 14-nm transistors used in flash memories a few years ago, according to industry experts.
Such a shift of importance from miniaturization to 3D technologies is likely to affect the industry's stance about the most difficult part of the chipmaking process, photolithography.
Photolithography is a process in which a circuit plan is imprinted on the photosensitized surface of a silicon wafer by beaming light toward the wafer through a glass plate called a photo mask on which the circuit plan images are drawn. This is like the traditional photo development process, where an image captured on transparent film is imprinted on paper by projecting light through the negative film toward the photosensitized paper.
As circuits further miniaturize, the process needs shorter-wave lights for better resolution. The most-advanced miniaturization requires invisible light of the extreme ultraviolet or EUV spectrum range.
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