Chinese semiconductor industry
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@FairAndUnbiased I'd like to ask you EUV optics. I'm fairly confident China can polish a Si/Mo mirror base to sub-nanometer roughness given that it can do so on a 4m SiC aspheric mirror, but how's China's physical vapour deposition? Is it accurate enough to deposit the Si/Mo layers to the requisite precision?
The tolerance isn't where it needs to be. For example, the surface roughness is better than 0.5nm. That needs to be better than 0.1nm, and preferably 0.05nm as mentioned here:
However, it's great that there's a commercial Chinese entity working on this. They should be able to improve their tolerance to the degree needed by the time the other components of the EUVL machine are ready.
HC Semitek: Small batch sampling and testing of 650V GaN products have been completed
Huacan Optoelectronics said in an agency survey that the company has completed small-batch sampling and testing of 650V GaN products, and the performance of 650V GaN MOSFETs can meet high-frequency AC requirements. /DC PD 65W fast charging application.
Regarding the question "Your company's GaN devices have been released since the fourth quarter of last year, but the results have not yet been released. Is there a possibility of defrauding investors?" Huacan Optoelectronics responded: The company has disclosed the GaN power in its regular reports. Progress of electronic devices: The company began to enter the field of GaN power electronic devices in 2020, and its products are mainly oriented to fast chargers for mobile consumer electronics terminals, other power supply equipment, cloud computing big data server centers, communications and automotive applications and other fields. In 2022, in terms of its own epitaxy, the research and development of 6-inch sapphire substrates has been started, and the research and development and tape-out of 650VGaN on Si for D-mode & E-mode epitaxial wafers have been initially completed. In terms of devices, small batch sampling and testing of 650V GaN products have been completed, and 650V GaN MOSFETs have been sampled. The performance can meet the high-frequency AC/DC PD 65W fast charging application, laying the foundation for the comprehensive launch of products in 2023.
Huacan Optoelectronics said in an agency survey that the company has completed small-batch sampling and testing of 650V GaN products, and the performance of 650V GaN MOSFETs can meet high-frequency AC requirements. /DC PD 65W fast charging application.
Regarding the question "Your company's GaN devices have been released since the fourth quarter of last year, but the results have not yet been released. Is there a possibility of defrauding investors?" Huacan Optoelectronics responded: The company has disclosed the GaN power in its regular reports. Progress of electronic devices: The company began to enter the field of GaN power electronic devices in 2020, and its products are mainly oriented to fast chargers for mobile consumer electronics terminals, other power supply equipment, cloud computing big data server centers, communications and automotive applications and other fields. In 2022, in terms of its own epitaxy, the research and development of 6-inch sapphire substrates has been started, and the research and development and tape-out of 650VGaN on Si for D-mode & E-mode epitaxial wafers have been initially completed. In terms of devices, small batch sampling and testing of 650V GaN products have been completed, and 650V GaN MOSFETs have been sampled. The performance can meet the high-frequency AC/DC PD 65W fast charging application, laying the foundation for the comprehensive launch of products in 2023.
Guangliwei: The T4000 model is expected to be introduced to the market in the second half of the year
Recently, Guangliwei said in an agency survey that in order to meet the needs of 6-inch, 8-inch and some 12-inch fabs for equipment cost-effectiveness, in 2022 we will start to develop general-purpose machines. The optimization and upgrade of the T4000 model is expected to be officially introduced to the market in the second half of this year.
In terms of wafer-level electrical testing equipment, Guangliwei's WAT testing machine has been put into the market to achieve mature applications and achieve high-speed growth in revenue benefits. In particular, the company's high-efficiency parallel WAT testing machine has been widely used in many domestic A 12-inch wafer factory and some design companies. At the same time, facing the field of wafer-level reliability testing, the company has expanded the research and development of wafer-level reliability testing (WLR) equipment, and has now achieved key function development and expanded the company's electrical testing equipment product line. In 2023, the T4000 model and reliability testing equipment will be put into the market for demo verification, application and promotion to help the business continue to grow.
In terms of semiconductor data software, on April 28, 2023, Guangliwei held the Semitronix DATAEXP User Forum in Shanghai, focusing on the difficulties of semiconductor big data analysis, sharing the new development of the DATAEXP big data analysis platform, and releasing the upgraded yield analysis management across the board , Defect analysis management, general data analysis management and other software have been recognized by customers participating in technical forums.
It is understood that Guangliwei is a leading supplier of integrated circuit EDA software and wafer-level electrical test equipment. The company focuses on chip yield improvement and electrical test rapid monitoring technology. An important partner of the enterprise. The company has now formed a full-process solution for yield improvement that combines EDA design software, WAT test equipment and semiconductor data analysis tools, and realizes the improvement of chip performance, yield, and stability in the entire product cycle from design to mass production of integrated circuits. promote.
In terms of wafer-level electrical testing equipment, Guangliwei's WAT testing machine has been put into the market to achieve mature applications and achieve high-speed growth in revenue benefits. In particular, the company's high-efficiency parallel WAT testing machine has been widely used in many domestic A 12-inch wafer factory and some design companies. At the same time, facing the field of wafer-level reliability testing, the company has expanded the research and development of wafer-level reliability testing (WLR) equipment, and has now achieved key function development and expanded the company's electrical testing equipment product line. In 2023, the T4000 model and reliability testing equipment will be put into the market for demo verification, application and promotion to help the business continue to grow.
In terms of semiconductor data software, on April 28, 2023, Guangliwei held the Semitronix DATAEXP User Forum in Shanghai, focusing on the difficulties of semiconductor big data analysis, sharing the new development of the DATAEXP big data analysis platform, and releasing the upgraded yield analysis management across the board , Defect analysis management, general data analysis management and other software have been recognized by customers participating in technical forums.
It is understood that Guangliwei is a leading supplier of integrated circuit EDA software and wafer-level electrical test equipment. The company focuses on chip yield improvement and electrical test rapid monitoring technology. An important partner of the enterprise. The company has now formed a full-process solution for yield improvement that combines EDA design software, WAT test equipment and semiconductor data analysis tools, and realizes the improvement of chip performance, yield, and stability in the entire product cycle from design to mass production of integrated circuits. promote.
this information is very hard to find because film smoothness is usually not something that the equipment vendor will just tell you, it is application and customer dependent. The RMS from polishing applies to the substrate surface so technically if you can polish the substrate flat enough, you can just use ALD. Not sure how molybdenum metal ALD is going in China. , but I don't know who is doing it on 4 m wide substrates. 4m is gigantic for a deposition substrate.
From the the 25th China Integrated Circuit Manufacturing Annual Conference
Wang Mengya, a senior technical expert of the 58th Research Institute of China Electronics Technology Group Corporation, gave a speech titled "Microsystem Reliability Design Based on Chip Integration Technology".
Chiplet, in fact, decomposes complex functions, and then develops a microchip with a single function that can be assembled modularly to build a microchip physical library. According to a jigsaw puzzle, the above-mentioned various microchips are mixed and integrated into an interposer, which is often called a silicon brick board to achieve some functions. Academician Xu, an authoritative domestic authority, defines chips as commercialized. Unpackaged bare chips with specific IP are packaged together through advanced integration technology like building blocks, mainly for the multiplexing of hard IP.
Through the above advanced definition, the development of chips mainly relies on two key technologies, one is advanced packaging technology to achieve physical interconnection between chips. It is possible to use IC processes such as common process, conventional process, and low-power process, and use the middle process of front-end and back-end integration to achieve a performance improvement. In fact, the design is more flexible, the cost is lower, and the cycle is shorter.
The other is the standard technology of the interface , which realizes the electrical interconnection between chips. In 2022, Intel, together with dozens of manufacturers such as AMD, released an open industry standard UcIe, which provides a high-bandwidth, low-latency, low-power, and low-cost packaging interconnection for Chiplets from different sources.
The reliability of microsystems based on chip integrated systems is also a difficult design difficulty. The reliability of the microsystem is analyzed from the aspects of design, process and detection.
In terms of design, it is necessary to carry out simulation tests of multiple physical scenarios such as electricity, heat, and force, and tests for signal integrity and power integrity.
In terms of technology, there are mainly wafer reconfiguration, wafer-level rewiring, wafer-level bump preparation, and three-dimensional stacking, etc., mainly focusing on several key technologies such as TSV, chip to wafer, RDL, and bump.
In terms of detection, the existing IEEE1838 standard mainly solves the interoperability and testability of the three-dimensional stacking of chips. It must be aimed at the particularity of microsystems. Based on the current integrated circuit test platform, it is necessary to praise a chip-based, micro-component , The multi-level test platform of the microsystem, and form the corresponding test methods and test specifications to ensure the reliability of the microsystem in all aspects.
The 58 Institute has a platform for the entire industrial chain in the field of integrated circuits, including a 7-nanometer design platform, a 65-nanometer mask platform, a national ceramic packaging center, a microsystem center line, etc., and has rich experience in the microsystem field. It has successively established 8-inch and 12-inch mid-way lines, and released the PDK of wafer-level fan-out packaging. A service platform for testing reliability, including 3D X-ray testing, scanning acoustic microscopy testing, etc.
Wang Mengya, a senior technical expert of the 58th Research Institute of China Electronics Technology Group Corporation, gave a speech titled "Microsystem Reliability Design Based on Chip Integration Technology".
Chiplet, in fact, decomposes complex functions, and then develops a microchip with a single function that can be assembled modularly to build a microchip physical library. According to a jigsaw puzzle, the above-mentioned various microchips are mixed and integrated into an interposer, which is often called a silicon brick board to achieve some functions. Academician Xu, an authoritative domestic authority, defines chips as commercialized. Unpackaged bare chips with specific IP are packaged together through advanced integration technology like building blocks, mainly for the multiplexing of hard IP.
Through the above advanced definition, the development of chips mainly relies on two key technologies, one is advanced packaging technology to achieve physical interconnection between chips. It is possible to use IC processes such as common process, conventional process, and low-power process, and use the middle process of front-end and back-end integration to achieve a performance improvement. In fact, the design is more flexible, the cost is lower, and the cycle is shorter.
The other is the standard technology of the interface , which realizes the electrical interconnection between chips. In 2022, Intel, together with dozens of manufacturers such as AMD, released an open industry standard UcIe, which provides a high-bandwidth, low-latency, low-power, and low-cost packaging interconnection for Chiplets from different sources.
The reliability of microsystems based on chip integrated systems is also a difficult design difficulty. The reliability of the microsystem is analyzed from the aspects of design, process and detection.
In terms of design, it is necessary to carry out simulation tests of multiple physical scenarios such as electricity, heat, and force, and tests for signal integrity and power integrity.
In terms of technology, there are mainly wafer reconfiguration, wafer-level rewiring, wafer-level bump preparation, and three-dimensional stacking, etc., mainly focusing on several key technologies such as TSV, chip to wafer, RDL, and bump.
In terms of detection, the existing IEEE1838 standard mainly solves the interoperability and testability of the three-dimensional stacking of chips. It must be aimed at the particularity of microsystems. Based on the current integrated circuit test platform, it is necessary to praise a chip-based, micro-component , The multi-level test platform of the microsystem, and form the corresponding test methods and test specifications to ensure the reliability of the microsystem in all aspects.
The 58 Institute has a platform for the entire industrial chain in the field of integrated circuits, including a 7-nanometer design platform, a 65-nanometer mask platform, a national ceramic packaging center, a microsystem center line, etc., and has rich experience in the microsystem field. It has successively established 8-inch and 12-inch mid-way lines, and released the PDK of wafer-level fan-out packaging. A service platform for testing reliability, including 3D X-ray testing, scanning acoustic microscopy testing, etc.
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