Chinese semiconductor industry

Status
Not open for further replies.

AndrewS

Brigadier
Registered Member
All flight computers on all aircraft and spacecraft are triple redundant, it is the absolute minimum for avionics regardless of RADHARD requirements. Here's an example of the published flight control system of the Boeing 747 which flew in the 1970s and was published in the 1990s.

Please, Log in or Register to view URLs content!

They still make chips RADHARD for a reason.

Understand the issues, the errors, etc.

Please, Log in or Register to view URLs content!

Yes, but the scenario I was responding was computational errors due to high-energy particles, rather than cumulative (and therefore permanent) damage due to prolonged radiation exposure

Look at the metrics. Say the performance hit is 50% as specified in the article.

Given the small size/weight of chips and plummeting launch costs, the point is that you're better off using a larger number of commercial chips with redundancy than going with really expensive radchips.
 

FairAndUnbiased

Brigadier
Registered Member
Yes, but the scenario I was responding was computational errors due to high-energy particles, rather than cumulative (and therefore permanent) damage due to prolonged radiation exposure

Look at the metrics. Say the performance hit is 50% as specified in the article.

Given the small size/weight of chips and plummeting launch costs, the point is that you're better off using a larger number of commercial chips with redundancy than going with really expensive radchips.
Please look up and understand the mechanisms of radiation damage to chips. Many RADHARD process changes like using a SOI structure have nothing to do with cumulative damage (total ionizing dose damage) or even soft errors, only catastrophic and destructive events like a latch up, single event induced burnout or single event induced gate rupture. 3 commercial chips voting doesn't prevent them from literally melting down to a latch up, they only prevent soft errors in the mildest of mild environments.

Please, Log in or Register to view URLs content!

How much does a rad hardened chip cost compared to launch costs? A tiny premium over using standard chips for a massive reduction in risk. What process are rad hardened chips fabricated on vs a leading edge chip? Large, cheap ones like 180 nm. What is the cost of a few 180 nm analog wafers at a contract fab or buying existing ones vs a space program?
 

FairAndUnbiased

Brigadier
Registered Member
Radiation hardened chips are less focused on the physical shielding of the chip with iron/lead/steel/etc (though they do have shunts that minimize ESD damage typical in high RAD environments), but primarily on 2 areas:

Error detection and recovery - similar to
Please, Log in or Register to view URLs content!
, but instead of guaranteeing data integrity, the radiation hardened chips assures computational integrity. This is done through methods such as having parallel circuits in the chip that both run the same instruction and checking if the outputs match or logic that runs the instructions multiple times and comparing the results. If the results are different(signaling radiation interference), then the chip itself reconciles the differences so the software doesn't crash or get invalid results.

Gate design differences - logic gates are typically larger or work at higher PN junction thresholds or use different doping agents to make them physically less susceptible to having a computational error when struck with a high energy particle.
The question was, why are circuits just not shielded. I answered the question exactly as posed - it is utterly impractical. I did not mention actual RADHARD techniques because it seemed outside the scope of the asker's knowledge.

You mentioned mostly software and architecture fixes, but the fundamental fix is process and materials. RADHARD chips use stuff like:

1. Running at higher gate voltage like 3.3V or 5V CMOS which requires larger gate size, metal line width, etc, but is less sensitive to ionization induced voltage spikes.

2. SOI process to prevent ionization induced shorts through the silicon substrate (latchups)

3. Exotic materials which are more resistant to voltage spikes such as SiC

The software and architecture fixes you mentioned only stop soft errors, they do not prevent the chip from lighting on fire from latch up events, gate rupture, burnout, etc.
 

paiemon

Junior Member
Registered Member
Please, Log in or Register to view URLs content!

Please, Log in or Register to view URLs content!
: SMEE的浸没式DUV光刻机测试机下线了,跟你在超大上说的一致,但是商用机还没有批产,有消息吗?
(any iDUV news?)

Please, Log in or Register to view URLs content!
: 今年,后来不是马上给封了俩月嘛
(The test machine is online this March.)
By this March, it means March of 2022? I just wanted to confirm I hadn't translated it incorrectly.
 

tokenanalyst

Brigadier
Registered Member

North Huachuang N7 project is about to fully complete the structural topping​


According to news from Weibo, Beijing Yizhuang, NAURA's N7 project is expected to fully complete the structural topping on December 25.

The project officially started in April this year , and the underground structure was fully capped in October . Up to now, 99% of the main structure construction project has been completed, and the secondary structure construction will be carried out in 2023, and it is expected to be completed in March 2024.

It is reported that after the completion of the project , it will become the largest equipment manufacturing base of NAURA , further improving the production scale and product capacity of NAURA in integrated circuit equipment, new semiconductor equipment, LED equipment, and photovoltaic equipment .

Please, Log in or Register to view URLs content!
 
Status
Not open for further replies.
Top