Assumptions you referenced from
@tinrobert is incorrect. 10DUV is not enough for 50K wpm of 28nm. No scanners or steppers available today is that fast. I will spare you the details since you are not going to believe me anyway.
But, you can go research:
- how many litho steps it take to make a 28nm wafer
- how fast a scanner/stepper can expose a wafer
- when ASML/Nikon/Canon/SMEE say for example 220 wph, the 'wafer' here means single exposure of a wafer
- by the way, this is the theoretical maximum throughput based on ideal conditions.
To be close to reality, you'll also need to consider (estimate) the scanner availability (uptime, utilization rate), wafer yield, wafer rework rate, etc.
Once you have all this info you could determine number of scanners required and conclude if my/
@tinrobert's estimate is correct.
28/45/55nm are all planar process. The total litho steps to build a chip is quite similar. The main differences is distribution of each layers of the chip between scanners of varying capabilities (iLine, KrF, ArF, ArFi).
Some variation do exist between the chip design and process. 28nm typically have a few more metal/via layers, so 45nm node would roughly be 44-46 litho steps. The difference are in the number of iLine layers and saving of $10M.
Besides, I'm sure SMIC already determine the intended product mix to come up with the $7 to 8B announced CAPEx. For reference, a true 100% 28nm fab like the on UMC is building in Singapore costs $3.6B for 30K wpm or $12B for 100K wpm.
I don't think SMIC ever took delivery of SSA600. SMIC did take delivery of a SSB600 a few years ago, but that tool was never qualified for HVM. I inferred from information from others in the industry that Yangdong may have took on the challenge to help SMEE qualify a 200mm SSA600/20.
I think you misunderstood what SSA600's true capability is. But that's okay, I have not seen anyone share anything of substance beyond the info ("claims") that's published on SMEE's website.
It's widely known in the industry SMEE reverse engineer the SSA600/10 off of ASML's old scanner. SSA600 is based on very old technology that was introduced in the late 1990s for 200mm wafers production. Looking at its 0.75NA lens, it was reverse engineered from ASML PAS5500/1150C. SMEE published many papers on SSA600/10 & SSA600/20 this past decade. Hardware, software, and specifications given in those papers are consistent with the 'reverse engineered' narrative.
The SSA600 was never qualified in the field by any fabs. But if it was verified to have met all its specifications, it would have:
- resolution limit of 90nm
- throughput of >130wph @ 200mm
- 300mm wafer has more area to cover than 200mm
- at tool acceptance condition, 300mm is based on 96 & 200mm on 46 exposure fields (in reality, fields/wafer number is generally higher so actual throughput on product will be lower)
- so if SSA600 is used on 300mm wafers the ideal tool acceptance test throughput specification would be closer to >65wph
- this (very low throughput) is why only a 20W 4KHz laser is required & used
In contrast, a modern day Nikon/ASML ArF scanners all have 0.93 NA with resolution limit around 65nm with throughput in excess of 230wph (300mm wafers).
Even the modern day Nikon/ASML/Canon KrF scanners have higher NA that ranges between 0.80 to 0.93 with resolution limit of 80nm and throughput up to 330wph.
With the old ArF technology, SSA600/20, even if it works properly, what would be its place in the fab. An ArF scanner that underperforms a KrF scanner with much larger Cost-per-wafer would have a hard time finding a niche in a HVM fab.
All specifications in this last subject matter/section could be compiled off public info online. I verified each of them while typing this up.
I'm speculating of course BUT with your entire business is on the line, they have to do some serious thinking to stay buoyant.
